具有串行并行Domino编码器的低功耗CMOS折叠和插值ADC

2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI:10.1109/EDSSC.2005.1635364

Zhen Liu, S. Jia, Zhongjian Chen, Xing Zhang, L. Ji

{"title":"具有串行并行Domino编码器的低功耗CMOS折叠和插值ADC","authors":"Zhen Liu, S. Jia, Zhongjian Chen, Xing Zhang, L. Ji","doi":"10.1109/EDSSC.2005.1635364","DOIUrl":null,"url":null,"abstract":"A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A serial-parallel Domino encoder (SPDE) is presented to reduce power dissipation. A special two-stage interpolation network is adopted to decrease static nonlinearity error. The total power dissipation is merely 80mW at a 5V supply.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low-Power CMOS Folding and Interpolating ADC with a Serial-Parallel Domino Encoder\",\"authors\":\"Zhen Liu, S. Jia, Zhongjian Chen, Xing Zhang, L. Ji\",\"doi\":\"10.1109/EDSSC.2005.1635364\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A serial-parallel Domino encoder (SPDE) is presented to reduce power dissipation. A special two-stage interpolation network is adopted to decrease static nonlinearity error. The total power dissipation is merely 80mW at a 5V supply.\",\"PeriodicalId\":429314,\"journal\":{\"name\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2005.1635364\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2005.1635364","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

设计了一种8位200MHz低功耗CMOS折叠插值模数转换器。提出了一种串行并行的Domino编码器(SPDE)来降低功耗。采用特殊的两级插补网络减小静态非线性误差。在5V电源下，总功耗仅为80mW。

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Low-Power CMOS Folding and Interpolating ADC with a Serial-Parallel Domino Encoder

A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A serial-parallel Domino encoder (SPDE) is presented to reduce power dissipation. A special two-stage interpolation network is adopted to decrease static nonlinearity error. The total power dissipation is merely 80mW at a 5V supply.

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来源期刊

2005 IEEE Conference on Electron Devices and Solid-State Circuits

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