Low-Power CMOS Folding and Interpolating ADC with a Serial-Parallel Domino Encoder

Abstract

A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A serial-parallel Domino encoder (SPDE) is presented to reduce power dissipation. A special two-stage interpolation network is adopted to decrease static nonlinearity error. The total power dissipation is merely 80mW at a 5V supply.