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2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications最新文献

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Algorithm Transformation for FPGA Implementation FPGA实现的算法转换
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.17
D. Bailey, C. T. Johnston
{"title":"Algorithm Transformation for FPGA Implementation","authors":"D. Bailey, C. T. Johnston","doi":"10.1109/DELTA.2010.17","DOIUrl":"https://doi.org/10.1109/DELTA.2010.17","url":null,"abstract":"High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by porting them to an FPGA based hardware implementation. Porting does not always result in efficient architectures as the original algorithms are usually developed and optimized to run on a serial processor. To obtain an efficient hardware architecture, one that makes use of the available parallelism, the algorithms need to be transformed. Eleven such transformations are identified and explained. While some of these are straightforward, and have been implemented by some compilers, many cannot be automated because they require detailed knowledge of the algorithm.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133085482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
An Efficient Hardware Implementation for a Reciprocal Unit 一种互易单元的高效硬件实现
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.65
Andreas Habegger, A. Stahel, J. Goette, M. Jacomet
{"title":"An Efficient Hardware Implementation for a Reciprocal Unit","authors":"Andreas Habegger, A. Stahel, J. Goette, M. Jacomet","doi":"10.1109/DELTA.2010.65","DOIUrl":"https://doi.org/10.1109/DELTA.2010.65","url":null,"abstract":"The computation of the reciprocal of a numerical value is an important ingredient of many algorithms. We present a compact hardware architecture to compute reciprocals by two or three Newton-Raphson iterations to obtain the accuracy of IEEE 754 single- and double-precision standard, respectively. We estimate the initialization value by a specially designed second-order polynomial approximating the reciprocal. By using a second-order polynomial, we succeed in using one single hardware architecture for both, the polynomial approximation computations as well as the Newton-Raphson iterations. Therefore, we obtain a most compact hardware implementation for the complete reciprocal computation.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"489 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133271626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An Exact and Efficient Critical Path Tracing Algorithm 一种精确高效的关键路径跟踪算法
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.35
A. Bosio, P. Girard, S. Pravossoudovitch, P. Bernardi, M. Reorda
{"title":"An Exact and Efficient Critical Path Tracing Algorithm","authors":"A. Bosio, P. Girard, S. Pravossoudovitch, P. Bernardi, M. Reorda","doi":"10.1109/DELTA.2010.35","DOIUrl":"https://doi.org/10.1109/DELTA.2010.35","url":null,"abstract":"This paper presents an exact and efficient Critical Path Tracing algorithm targeting fault simulation of both Transition and Stuck-at faults. The complexity of the proposed algorithm is linear in the number of gates traced during the path tracing process. Experimental results show the efficiency of the proposed approach on a set of benchmark circuits.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121363368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Inverse Neural MIMO NARX Model Identification of Nonlinear System Optimized with PSO PSO优化非线性系统的逆神经MIMO NARX模型辨识
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.61
H. Anh, N. Phuc
{"title":"Inverse Neural MIMO NARX Model Identification of Nonlinear System Optimized with PSO","authors":"H. Anh, N. Phuc","doi":"10.1109/DELTA.2010.61","DOIUrl":"https://doi.org/10.1109/DELTA.2010.61","url":null,"abstract":"In this paper, a neural Inverse Dynamic MIMO NARX (Neural IDMN) model is applied for modelling and identifying simultaneously both of joints of the prototype 2- axes PAM robot arm. The contact force variations and highly nonlinear coupling features of both links of the 2-axes PAM system are modelled thoroughly through an Inverse Neural MIMO NARX Model-based identification process using experiment input-output training data. For the first time, the parameters of dynamic Inverse neural MIMO NARX Model of the 2-axes PAM robot arm has been identified and optimized with Particle Swarm optimisation (PSO) algorithm. The results show that the neural IDMN Model trained by PSO algorithm yields outstanding performance and perfect accuracy.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128637707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
DVCC-Based Voltage-Mode Biquadratic Filter with High-Input Impedance 基于dvcc的高输入阻抗电压型双二次滤波器
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.51
Wei-Yuan Chiu, Jiun-Wei Horng, Hu-Chan Lee, Chen-Chuan Huang
{"title":"DVCC-Based Voltage-Mode Biquadratic Filter with High-Input Impedance","authors":"Wei-Yuan Chiu, Jiun-Wei Horng, Hu-Chan Lee, Chen-Chuan Huang","doi":"10.1109/DELTA.2010.51","DOIUrl":"https://doi.org/10.1109/DELTA.2010.51","url":null,"abstract":"A high-input impedance voltage-mode universal biquadratic filter with one-input and five-outputs is presented. The proposed circuit uses three plus-type differential voltage current conveyors (DVCCs), two grounded capacitors and three resistors and offers the following features: the realization of all the standard filter functions, that is, high-pass, band-pass, low-pass, notch, and all-pass filters, orthogonal control of omega o and Q, the use of only grounded capacitors, high-input impedance and low active and passive sensitivities.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116100307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Notations for Multiphase Pipelines 多相管道符号
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.29
C. T. Johnston, D. Bailey, P. Lyons
{"title":"Notations for Multiphase Pipelines","authors":"C. T. Johnston, D. Bailey, P. Lyons","doi":"10.1109/DELTA.2010.29","DOIUrl":"https://doi.org/10.1109/DELTA.2010.29","url":null,"abstract":"FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture for supporting the required high throughput. Although pipelining is a well known technique for hardware design and is simple to describe, our experience has been that people have many problems implementing working pipelines, especially for multiphase designs. Existing hardware description languages force developers to design pipelines as a special case of parallel architecture, which makes it difficult to ensure that the pipeline has internally consistent timing. This is especially problematic in multiphase pipelines. This paper shows how many of these problems may be overcome by basing the notation on sequential dataflow, and discusses control issues of priming, stalling and flushing, with a proposed compiler implementation.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125547580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Least-squares Optimal Interpolation for Fast Image Super-resolution 快速图像超分辨率的最小二乘最优插值
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.59
A. Gilman, D. Bailey, S. Marsland
{"title":"Least-squares Optimal Interpolation for Fast Image Super-resolution","authors":"A. Gilman, D. Bailey, S. Marsland","doi":"10.1109/DELTA.2010.59","DOIUrl":"https://doi.org/10.1109/DELTA.2010.59","url":null,"abstract":"Image super-resolution is generally regarded as consisting of three steps – image registration, fusion, and deblurring. This paper presents a novel technique for resampling a non-uniformly sampled image onto a uniform grid that can be used for fusion of translated input images. The proposed method can be very fast, as it can be implemented as a finite impulse response filter of low order (10th order results in good performance). The technique is based on optimising the resampling filter coefficients using a simple image model in a least squares fashion. The method is tested experimentally on a range of images and shown to have similar results to that of a least-squares optimal filter. Further experimental comparisons are made against a number of methods commonly used in image super-resolution that show that the proposed method is superior to these.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129706372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Integrated Multiplexer for Nerve Electrodes 神经电极集成多路复用器
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.72
Z. Lertmanorat, D. Durand
{"title":"Integrated Multiplexer for Nerve Electrodes","authors":"Z. Lertmanorat, D. Durand","doi":"10.1109/DELTA.2010.72","DOIUrl":"https://doi.org/10.1109/DELTA.2010.72","url":null,"abstract":"Multiple contact nerve cuff electrodes require many leads, making their implantation difficult and potentially damaging to the nerve. Therefore the design of circuits capable of reducing the number of wires is crucial to the development of a device that can be implanted in patients. The flat interface nerve electrode (FINE) was developed to allow selective recording and selective stimulation capabilities. We report here the design of multiplexers embedded within the cuff electrode that can reduce the number of leads needed to control thirty two channels. The electrode design includes thirty-two contacts in a 1mmx8mm opening. Each contact size is 300μm x400μm with access resistance less than 1kW. The control circuit was implemented on a polyimide film using off the-shelf surface mounted electronic components. The electronic module was mounted directly onto the electrode’s flat substrate. Two control circuit implementations for the control of the thirty two channels were designed, built and tested; 1) a single supply design with only two wires but limited to cathodic-first pulse and 2) a dual-supply design requiring three lead wires but an arbitrary stimulation waveform. These circuit designs allow a significant reduction of the number of leads required for the control of the electrode. However, the hermetic sealing of the devices has not yet been implemented. (Funding was provided the National Institutes of Health, grant number 5R01NS032845-14.)","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132275584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A More Precise Model of Noise Based PCMOS Errors 基于噪声的PCMOS误差更精确的模型
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.18
A. Bhanu, Mark S. K. Lau, K. Ling, V. Mooney, Anshul Singh
{"title":"A More Precise Model of Noise Based PCMOS Errors","authors":"A. Bhanu, Mark S. K. Lau, K. Ling, V. Mooney, Anshul Singh","doi":"10.1109/DELTA.2010.18","DOIUrl":"https://doi.org/10.1109/DELTA.2010.18","url":null,"abstract":"In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder. Our contribution helps account for the filtering effect seen in noise based PCMOS in a novel way. The characterization proposed here can enable accurate multi-bit models based on fast mathematical extrapolation instead of expensive and slow HSPICE simulations.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132371130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Enabling False Path Identification from RTL for Reducing Design and Test Futileness 从RTL中启用错误路径识别，以减少设计和测试的无效性
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.23
Hiroshi Iwata, S. Ohtake, H. Fujiwara
{"title":"Enabling False Path Identification from RTL for Reducing Design and Test Futileness","authors":"Hiroshi Iwata, S. Ohtake, H. Fujiwara","doi":"10.1109/DELTA.2010.23","DOIUrl":"https://doi.org/10.1109/DELTA.2010.23","url":null,"abstract":"Information on false paths is useful for design and test. Since identification of false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established only by some restricted logic synthesis. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125527534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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