Enabling False Path Identification from RTL for Reducing Design and Test Futileness

Abstract

Information on false paths is useful for design and test. Since identification of false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established only by some restricted logic synthesis. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis.