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2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications最新文献

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A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques 基于时域技术的低功耗关联处理器与第r个最接近匹配汉明距离搜索引擎
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.37
Trong-Tu Bui, T. Shibata
{"title":"A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques","authors":"Trong-Tu Bui, T. Shibata","doi":"10.1109/DELTA.2010.37","DOIUrl":"https://doi.org/10.1109/DELTA.2010.37","url":null,"abstract":"In this paper, a low-power Hamming distance associative processor employing time-domain techniques has been developed focusing on the implementation of an r-th nearest-match location identification function. The architecture not only inherits advantages of analog implementations on power consumption but also improves the accuracy of such implementations. This is because it employs digital technique for distance comparison and delay-time technique for searching for the r-th nearest-match template word. A 64-bit 32-word proof-of-concept chip has been designed and fabricated in a 0.18-um CMOS process and has been successfully tested. Power consumption is below 1.8 mW and core size is 0.65x0.445 mm2, respectively.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114175101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Independent Component Analysis Applied to Watermark Extraction and its Implemented Model on FPGAs 独立分量分析在水印提取中的应用及其fpga实现模型
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.39
T. Le-Tien, Dien Vo-Ngoc, Lan Ngo-Hoang, Sungyoung Lee
{"title":"Independent Component Analysis Applied to Watermark Extraction and its Implemented Model on FPGAs","authors":"T. Le-Tien, Dien Vo-Ngoc, Lan Ngo-Hoang, Sungyoung Lee","doi":"10.1109/DELTA.2010.39","DOIUrl":"https://doi.org/10.1109/DELTA.2010.39","url":null,"abstract":"Most of published audio watermark algorithms are suffered a trade-off between inaudibility and detectibility, and the detection performance depends greatly on the strength of noise added by communication channels. This work introduces an audio watermarking method that can overcome this challenge, i.e. allows increasing watermark strength while preserving inaudibility. The scheme uses psychoacoustic masking compatible to MPEG layer 1 Model 1 and adjusts it in a data adaptive way. A blind watermark extraction technique using the Independent Component Analysis (ICA) is shown to minimize the watermark decoding error. An implementation of a simple quantization-based watermarking algorithm (LSB) on the Spartan-3 FPGA Starter Kit of Xilinx is also presented as a part of hardware demonstration of the method.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123880461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluating the Performance of Different Classification Algorithms for Fabricated Semiconductor Wafers 评价不同分类算法对半导体晶圆的性能
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.69
Jian Wei Cheng, M. Ooi, Chris Chan, Y. Kuang, S. Demidenko
{"title":"Evaluating the Performance of Different Classification Algorithms for Fabricated Semiconductor Wafers","authors":"Jian Wei Cheng, M. Ooi, Chris Chan, Y. Kuang, S. Demidenko","doi":"10.1109/DELTA.2010.69","DOIUrl":"https://doi.org/10.1109/DELTA.2010.69","url":null,"abstract":"Defect detection and classification is crucial in ensuring product quality and reliability. Classification provides information on problems related to the detected defects which can then be used to perform yield prediction, fault diagnosis, correcting manufacturing issues and process control. Accurate classification requires good selection of features to help distinguish between different cluster types. This research investigates the use of two features for classification: Polar Fourier Transform (PFT) and image Rotational Moment Invariant (RMI). It provides a comprehensive critical evaluation of several classification schemes in terms of performance and accuracy based on these features. It concludes by discussing the suitability of each classifier for classifying different types of defect clusters on fabricated semiconductor wafers.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122274254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Very High Q, NEMS Inductor for 12GHz Wireless Sensor Applications 用于12GHz无线传感器的超高Q, NEMS电感器
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.45
N. Khalid, J. Singh, H. Le, K. Shah, J. Devlin, Z. Sauli
{"title":"Very High Q, NEMS Inductor for 12GHz Wireless Sensor Applications","authors":"N. Khalid, J. Singh, H. Le, K. Shah, J. Devlin, Z. Sauli","doi":"10.1109/DELTA.2010.45","DOIUrl":"https://doi.org/10.1109/DELTA.2010.45","url":null,"abstract":"This paper presents the design and optimisation of high quality (Q) factor inductors using Micro/Nano Electro-Mechanical Systems (NEMS/MEMS) technology for 10GHz to 20GHz frequency band. Three inductors have been designed with rectangular, circular and symmetric topologies. Comparison has been made amongst the three to determine the best Q-factor. Inductors are designed on Silicon-on-Sapphire (SOS) because of its advantages including high resistivity and low parasitic capacitance. The effects of various parameters such as outer diameter (OD), the width of metal traces (W), the thickness of the metal (T) and the air gap (AG) on the Q-factor and inductance performances are thoroughly investigated. Results indicate that the symmetric inductor has highest Q-factor with peak Q of 192 at 12GHz for a 1.13nH.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132559922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fast and Accurate Automatic Defect CLuster Extraction for Semiconductor Wafers 快速准确的半导体晶圆缺陷簇自动提取
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.66
M. Ooi, Chris Chan, W. J. Tee, Y. Kuang, L. Kleeman, S. Demidenko
{"title":"Fast and Accurate Automatic Defect CLuster Extraction for Semiconductor Wafers","authors":"M. Ooi, Chris Chan, W. J. Tee, Y. Kuang, L. Kleeman, S. Demidenko","doi":"10.1109/DELTA.2010.66","DOIUrl":"https://doi.org/10.1109/DELTA.2010.66","url":null,"abstract":"Reduction in integrated circuit (IC) half technology, which will no longer be sustainable by traditional fault isolation and failure analysis techniques. There is an urgent need for diagnostic software tools with (which manifest as clusters) observed from manufacturing defects can be traced back to a specific process, equipment or technology, a novel data mining algorithm defects from test data logs. This algorithm and provides accurate detection of 99%.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131008027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems (若干)在复杂异构集成系统中纳入BIST的开放问题
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.67
Manuel J. Barragan Asian, G. Huertas, A. Rueda, J. Huertas
{"title":"(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems","authors":"Manuel J. Barragan Asian, G. Huertas, A. Rueda, J. Huertas","doi":"10.1109/DELTA.2010.67","DOIUrl":"https://doi.org/10.1109/DELTA.2010.67","url":null,"abstract":"This paper presents an overview of test techniques that offer promising features when Built-In-Self-Test (BIST) must be applied to complex intgrated systems including analog, mixed-signal and RF parts. Emphasis is on techniques exhibiting a good trade-off between test requirements (basically in terms of signal accuracy and frequency) and test quality.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125864850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Massively Parallel Cuckoo Pattern Matching Applied for NIDS/NIPS 大规模并行杜鹃模式匹配应用于NIDS/NIPS
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.46
T. Tran, S. Kittitornkun
{"title":"Massively Parallel Cuckoo Pattern Matching Applied for NIDS/NIPS","authors":"T. Tran, S. Kittitornkun","doi":"10.1109/DELTA.2010.46","DOIUrl":"https://doi.org/10.1109/DELTA.2010.46","url":null,"abstract":"This paper describes a Cuckoo-based Pattern Matching (CPM) engine based on a recently developed hashing algorithm called Cuckoo Hashing. We implement the improved parallel Cuckoo Hashing suitable for hardware-based multi-pattern matching with arbitrary length. CPM can rapidly update the static pattern set without reconfiguration while consuming the lowest amount of hardware. With the power of massively parallel processing, the speedup of CPM is up to 128X as compared with serial Cuckoo implementation. Compared to other hardware systems, CPM is far better in performance and saves 30% of the area.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130977788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Wide Band Linear Voltage-to-Current Converter Design 宽带线性电压-电流变换器设计
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.24
C. Lin, Sheng-Feng Lin, Chi Fu Wang
{"title":"Wide Band Linear Voltage-to-Current Converter Design","authors":"C. Lin, Sheng-Feng Lin, Chi Fu Wang","doi":"10.1109/DELTA.2010.24","DOIUrl":"https://doi.org/10.1109/DELTA.2010.24","url":null,"abstract":"In this work, we propose a wide band linear voltage-to-current converter (VIC) with mobility degradation compensation. By use of NMOS output stage and grounding NMOS input stage, PSRR enhances as well as body effect decreases. In addition, through utilizing the sum of two current sources operate in linear and saturation region respectively, the nonlinearity of complementary parabolic voltage to current characteristics caused by mobility degradation are reduced. A feedback loop is then inserted to increase bandwidth, so that the proposed VIC is useful in further applications. A practical chip was fabricated by TSMC 0.35 3.3V CMOS process with its measured transconductance, bandwidth, and operational range are 0.975~1.032, 85.5MHz, and 1.2V respectively. The experiment results show that the proposed design significantly improves bandwidth and the nonlinearity effect of VIC originated from mobility degradation.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130479995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs soc内建自修复ram的测试与维修计划
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.42
Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou
{"title":"Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs","authors":"Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou","doi":"10.1109/DELTA.2010.42","DOIUrl":"https://doi.org/10.1109/DELTA.2010.42","url":null,"abstract":"Built-in self-repair (BISR) is one promising approach for improving the yield of memory cores in an system-on-chip (SOC). This paper presents a test scheduling approach for BISR memory cores under the constraint of maximum power consumption. An efficient test scheduling algorithm based on the early-abort probability is proposed. Experimental results show that the scheduled results of the proposed algorithm have lower expected test time in comparison with the previous work. For ITC’02 benchmarks, for example, about 10.7% average reduction ratio of expected test time can be achieved by the proposed algorithm.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"364 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121654200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA 在赛灵思FPGA上实现异步电路的无害化穆勒门
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.40
C. Pham-Quoc, Anh-Vu Dinh-Duc
{"title":"Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA","authors":"C. Pham-Quoc, Anh-Vu Dinh-Duc","doi":"10.1109/DELTA.2010.40","DOIUrl":"https://doi.org/10.1109/DELTA.2010.40","url":null,"abstract":"Asynchronous circuits are more and more predominant because their advantages in comparison with synchronous circuits. While asynchronous circuits can be implemented in custom VLSI, their fabricated-time is too long to allow rapid prototyping. Meanwhile, FPGA devices are dominant implementation media for digital circuits. Unfortunately, they do not support asynchronous circuits because of the lack of asynchronous circuit elements such as Muller gates, etc. This paper proposes a new efficient technique to build hazard-free Muller gates on Xilinx FPGA. Timing and/or area constraints for place and route process are generated to avoid hazard. The hazard-free Muller gates are predefined in libraries in HDL. These gates could be used to implement asynchronous circuits on FPGA. The developed technique is done with Xilinx but could be applied to others LUT-based FPGA families. An efficient design flow to implementing asynchronous circuits on Xilinx FPGA using the hazard-free Muller gates is presented also.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134404265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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