Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA

Abstract

Asynchronous circuits are more and more predominant because their advantages in comparison with synchronous circuits. While asynchronous circuits can be implemented in custom VLSI, their fabricated-time is too long to allow rapid prototyping. Meanwhile, FPGA devices are dominant implementation media for digital circuits. Unfortunately, they do not support asynchronous circuits because of the lack of asynchronous circuit elements such as Muller gates, etc. This paper proposes a new efficient technique to build hazard-free Muller gates on Xilinx FPGA. Timing and/or area constraints for place and route process are generated to avoid hazard. The hazard-free Muller gates are predefined in libraries in HDL. These gates could be used to implement asynchronous circuits on FPGA. The developed technique is done with Xilinx but could be applied to others LUT-based FPGA families. An efficient design flow to implementing asynchronous circuits on Xilinx FPGA using the hazard-free Muller gates is presented also.