发布求助
文献互助 智能选刊 最新文献

2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications最新文献

筛选
英文 中文
A Smart CMOS Image Sensor with On-chip Hot Pixel Correcting Readout Circuit for Biomedical Applications 具有片上热像素校正读出电路的生物医学应用智能CMOS图像传感器
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.36
Yuan Cao, Fang Tang, A. Bermak, T. M. Le
{"title":"A Smart CMOS Image Sensor with On-chip Hot Pixel Correcting Readout Circuit for Biomedical Applications","authors":"Yuan Cao, Fang Tang, A. Bermak, T. M. Le","doi":"10.1109/DELTA.2010.36","DOIUrl":"https://doi.org/10.1109/DELTA.2010.36","url":null,"abstract":"One of the most recent and exciting applications for CMOS image sensors is in the biomedical field. In such applications, these sensors often operate in harsh environments (high intensity, high pressure, long time exposure), which increase the probability for the occurrence of hot pixel defects over their lifetime. This paper presents a novel smart CMOS image sensor integrating hot pixel correcting readout circuit to preserve the quality of the captured images. With this approach, no extra non-volatile memory is required in the sensor device to store the locations of the hot pixels. In addition, the reliability of the sensor is ensured by maintaining a real-time detection of hot pixels during image capture.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134484071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Routing and Tracking System for Mobile Vehicles in Large Area 大范围机动车辆路径与跟踪系统
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.38
T. Le-Tien, Vu Phung-The
{"title":"Routing and Tracking System for Mobile Vehicles in Large Area","authors":"T. Le-Tien, Vu Phung-The","doi":"10.1109/DELTA.2010.38","DOIUrl":"https://doi.org/10.1109/DELTA.2010.38","url":null,"abstract":"The paper describes a practical model for routing and tracking with mobile vehicle in a large area outdoor environment based on the Global Positioning System (GPS) and Global System for Mobile Communication (GSM). The supporting devices, GPS module-eMD3620 of AT&S company and GSM modem-GM862 of Telit company, are controlled by a 32bits microcontroller LM3S2965 implemented a new version ARM Cortex M3 core. The system is equipped the Compass sensor-YAS529 of Yamaha company and Accelerator sensor- KXSC72050 of Koinix company to determine moving direction of a vehicle. The device will collect positions of the vehicle via GPS receiver and then sends the data of positions to supervised center by the SMS (Short Message Services) or GPRS (General Package Radio Service) service. The supervised center is composed of a development kit that supports GSM techniques-WMP100 of the Wavecom company. After processing data, the position of the mobile vehicle will be displayed on Google Map.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122032843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology 基于sub- 32nm双栅MOS技术的创新6T混合SRAM单元
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.54
A. Amara, B. Giraud, O. Thomas
{"title":"An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology","authors":"A. Amara, B. Giraud, O. Thomas","doi":"10.1109/DELTA.2010.54","DOIUrl":"https://doi.org/10.1109/DELTA.2010.54","url":null,"abstract":"This paper presents a new SRAM memory cell in Double Gate MOS technology. It’s a reconfigurable 6T-4T that takes benefit of the advantages of both 6T and 4T SRAM cells. The cell improves both read stability and write-ability, without adding any transistor or external signal, compared to conventional 6T SRAM cell. The write ability is improved by a factor of 64% and the stability in read mode by a factor of 70% while slightly increasing the stability in retention mode. Thanks to its excellent stability and good insensitivity to process variations (δ/μµ 4 and 2 times lower), the proposed architecture is also a promising candidate for low voltage applications.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126286901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Virtual Instrumentation Based IC Parametric Tester for Engineering Education 基于虚拟仪器的工程教育集成电路参数测试仪
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.71
Loren Nolan, M. Chew, S. Demidenko, M. Ooi
{"title":"Virtual Instrumentation Based IC Parametric Tester for Engineering Education","authors":"Loren Nolan, M. Chew, S. Demidenko, M. Ooi","doi":"10.1109/DELTA.2010.71","DOIUrl":"https://doi.org/10.1109/DELTA.2010.71","url":null,"abstract":"Importance of training in electronic test technology within a wider electronic education framework has been acknowledged and extensively discussed in the literature. The main difficulty in incorporating test technology education and training into a curriculum of an electronic engineering degree offered by higher education institutions is an extremely high cost of industry-grate automated test equipment. Trying to address this shortcoming, this paper proposes a fully operational prototype of a simple low-cost programmable electronic test system for functional and DC parametric testing of simple logic ICs. The system is based on National Instruments tools and software. It has been developed to aid teaching of undergraduate units ECE4064 Electronic Test Technology offered at Monash University, Malaysia and 143 .457 Advanced Micro Technologies offered at Massey University, New Zealand.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"121 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129407769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Four-Stage Design Approach Towards Securing a Vehicular Ad Hoc Networks Architecture 一种保护车载自组织网络架构的四阶段设计方法
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.49
Raghu Sunnadkal, B. Soh, H. Phan
{"title":"A Four-Stage Design Approach Towards Securing a Vehicular Ad Hoc Networks Architecture","authors":"Raghu Sunnadkal, B. Soh, H. Phan","doi":"10.1109/DELTA.2010.49","DOIUrl":"https://doi.org/10.1109/DELTA.2010.49","url":null,"abstract":"In this paper we propose a four-stage design approach towards securing a VANET architecture with an improved PKI structure. The new PKI structure helps in keeping the users autonomous, whilst achieving the security alongside. Communication between the central certificate authority is minimized by employing self authorization by the users. This is attained by self generation of pseudonyms. This scheme will help in providing the security to users when not in coverage with the central certificate authority. The paper also proposes an efficient way of deploying CRL’s during revocation scheme which employs car-to-car forwarding of CRL’s along with the RSU’s.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124563763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
FPGA Implementation of a Real Time Maximum Likelihood Space-Time Decoder on a MIMO Software Radio Test Platform MIMO软件无线电测试平台上实时最大似然空时解码器的FPGA实现
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.9
P. J. Green, Desmond P. Taylor
{"title":"FPGA Implementation of a Real Time Maximum Likelihood Space-Time Decoder on a MIMO Software Radio Test Platform","authors":"P. J. Green, Desmond P. Taylor","doi":"10.1109/DELTA.2010.9","DOIUrl":"https://doi.org/10.1109/DELTA.2010.9","url":null,"abstract":"This paper describes the concept, architecture, development and demonstration of a real time, maximum likelihood Alamouti decoder for a wireless 4-transmit 4-receiver multiple input and multiple output (MIMO) Smart Antenna Software Radio Test System (SASRATS) platform. It is implemented on a Xilinx Virtex 2 Pro Field Programmable Gate Array (FPGA).Hardware, firmware, use of the Xilinx Core Generator Intellectual Property modules and experimental verification of the decoder are discussed.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115791010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An ECG-on-Chip for Wearable Cardiac Monitoring Devices 用于可穿戴心脏监测设备的片上心电图
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.43
Deepu John, Xiaoyuan Xu, X. Zou, L. Yao, Y. Lian
{"title":"An ECG-on-Chip for Wearable Cardiac Monitoring Devices","authors":"Deepu John, Xiaoyuan Xu, X. Zou, L. Yao, Y. Lian","doi":"10.1109/DELTA.2010.43","DOIUrl":"https://doi.org/10.1109/DELTA.2010.43","url":null,"abstract":"This paper describes a highly integrated, low power chip solution for ECG signal processing in wearable devices. The chip contains an instrumentation amplifier with programmable gain, a band-pass filter, a 12-bit SAR ADC, a novel QRS detector, 8K on-chip SRAM, and relevant control circuitry and CPU interfaces. The analog front end circuits accurately senses and digitizes the raw ECG signal, which is then filtered to extract the QRS. The sampling frequency used is 256 Hz. ECG samples are buffered locally on an asynchronous FIFO and is read out using a faster clock, as and when it is required by the host CPU via an SPI interface. The chip was designed and implemented in 0.35µm standard CMOS process. The analog core operates at 1V while the digital circuits and SRAM operate at 3.3V. The chip total core area is 5.74 mm2 and consumes 9.6µW. Small size and low power consumption make this design suitable for usage in wearable heart monitoring devices.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123766317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor 可靠可重构多核处理器基础IP可靠性管理器设计
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.57
H. Kerkhoff, Xiao Zhang
{"title":"Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor","authors":"H. Kerkhoff, Xiao Zhang","doi":"10.1109/DELTA.2010.57","DOIUrl":"https://doi.org/10.1109/DELTA.2010.57","url":null,"abstract":"Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of safety-critical applications, these processors must have an ultra high dependability. This paper discusses the design and verification of an infrastructural IP, the Dependability Manager, which takes care of most essential dependability issues. Several additional innovative approaches with regard to dependability have been incorporated, like the NoC, wrapper and Network Interface design. The Dependability Manager design has been verified on an FPGA and is being processed in UMC CMOS technology as part of a many-core processor.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132764434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 75dB-gain Low-power, Low-noise Amplifier for Low-frequency Bio-signal Recording 一种用于低频生物信号记录的75db增益低功耗低噪声放大器
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.20
D. Salhi, B. Godara
{"title":"A 75dB-gain Low-power, Low-noise Amplifier for Low-frequency Bio-signal Recording","authors":"D. Salhi, B. Godara","doi":"10.1109/DELTA.2010.20","DOIUrl":"https://doi.org/10.1109/DELTA.2010.20","url":null,"abstract":"This paper presents a low voltage, low noise and very low frequency amplifier suitable for bio-signal recording. The amplifier requires only ± 0.6V supply and consumes 1.24µW, with a 75.5 dB gain over a bandwidth covering a range of frequencies from some hundreds of mHz to 19kHz. A UMC 0.13µm CMOS process is used in design and simulation. The new solution is suitable for a variety of biomedical applications.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116885538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Modeling of Probabilistic Ripple-Carry Adders 概率纹波进位加法器的建模
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.14
Mark S. K. Lau, K. Ling, Y. Chu, A. Bhanu
{"title":"Modeling of Probabilistic Ripple-Carry Adders","authors":"Mark S. K. Lau, K. Ling, Y. Chu, A. Bhanu","doi":"10.1109/DELTA.2010.14","DOIUrl":"https://doi.org/10.1109/DELTA.2010.14","url":null,"abstract":"This paper proposes a mathematical model for probabilistic ripple-carry adders. The model gives explicit expressions for calculating error probabilities of sum and carry bits. The expressions show how errors propagate through the carry, which accumulate and eventually influence the correctness of a ripple-carry adder's outputs. The proposed model is flexible since it only requires mild assumptions on the probability distribution of noise. Hence, in addition to Gaussian, it is applicable to a wide class of distributions. We validate the model through HSPICE simulation. The model is able to predict error-rates of a simulated probabilistic ripple-carry adder with reasonable accuracy.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116921091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信