MIMO软件无线电测试平台上实时最大似然空时解码器的FPGA实现

2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI:10.1109/DELTA.2010.9

P. J. Green, Desmond P. Taylor

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引用次数: 3

摘要

本文介绍了一种用于无线4发4收多输入多输出(MIMO)智能天线软件无线电测试系统(SASRATS)平台的实时、最大似然Alamouti解码器的概念、结构、开发和演示。它是在Xilinx Virtex 2 Pro现场可编程门阵列(FPGA)上实现的。讨论了硬件、固件、Xilinx Core Generator知识产权模块的使用以及解码器的实验验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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FPGA Implementation of a Real Time Maximum Likelihood Space-Time Decoder on a MIMO Software Radio Test Platform

This paper describes the concept, architecture, development and demonstration of a real time, maximum likelihood Alamouti decoder for a wireless 4-transmit 4-receiver multiple input and multiple output (MIMO) Smart Antenna Software Radio Test System (SASRATS) platform. It is implemented on a Xilinx Virtex 2 Pro Field Programmable Gate Array (FPGA).Hardware, firmware, use of the Xilinx Core Generator Intellectual Property modules and experimental verification of the decoder are discussed.

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2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications

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