{"title":"基于sub- 32nm双栅MOS技术的创新6T混合SRAM单元","authors":"A. Amara, B. Giraud, O. Thomas","doi":"10.1109/DELTA.2010.54","DOIUrl":null,"url":null,"abstract":"This paper presents a new SRAM memory cell in Double Gate MOS technology. It’s a reconfigurable 6T-4T that takes benefit of the advantages of both 6T and 4T SRAM cells. The cell improves both read stability and write-ability, without adding any transistor or external signal, compared to conventional 6T SRAM cell. The write ability is improved by a factor of 64% and the stability in read mode by a factor of 70% while slightly increasing the stability in retention mode. Thanks to its excellent stability and good insensitivity to process variations (δ/μµ 4 and 2 times lower), the proposed architecture is also a promising candidate for low voltage applications.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"170 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology\",\"authors\":\"A. Amara, B. Giraud, O. Thomas\",\"doi\":\"10.1109/DELTA.2010.54\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new SRAM memory cell in Double Gate MOS technology. It’s a reconfigurable 6T-4T that takes benefit of the advantages of both 6T and 4T SRAM cells. The cell improves both read stability and write-ability, without adding any transistor or external signal, compared to conventional 6T SRAM cell. The write ability is improved by a factor of 64% and the stability in read mode by a factor of 70% while slightly increasing the stability in retention mode. Thanks to its excellent stability and good insensitivity to process variations (δ/μµ 4 and 2 times lower), the proposed architecture is also a promising candidate for low voltage applications.\",\"PeriodicalId\":421336,\"journal\":{\"name\":\"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications\",\"volume\":\"170 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-01-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DELTA.2010.54\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DELTA.2010.54","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology
This paper presents a new SRAM memory cell in Double Gate MOS technology. It’s a reconfigurable 6T-4T that takes benefit of the advantages of both 6T and 4T SRAM cells. The cell improves both read stability and write-ability, without adding any transistor or external signal, compared to conventional 6T SRAM cell. The write ability is improved by a factor of 64% and the stability in read mode by a factor of 70% while slightly increasing the stability in retention mode. Thanks to its excellent stability and good insensitivity to process variations (δ/μµ 4 and 2 times lower), the proposed architecture is also a promising candidate for low voltage applications.