An Efficient Hardware Implementation for a Reciprocal Unit

Andreas Habegger, A. Stahel, J. Goette, M. Jacomet
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引用次数: 14

Abstract

The computation of the reciprocal of a numerical value is an important ingredient of many algorithms. We present a compact hardware architecture to compute reciprocals by two or three Newton-Raphson iterations to obtain the accuracy of IEEE 754 single- and double-precision standard, respectively. We estimate the initialization value by a specially designed second-order polynomial approximating the reciprocal. By using a second-order polynomial, we succeed in using one single hardware architecture for both, the polynomial approximation computations as well as the Newton-Raphson iterations. Therefore, we obtain a most compact hardware implementation for the complete reciprocal computation.
一种互易单元的高效硬件实现
数值倒数的计算是许多算法的重要组成部分。我们提出了一个紧凑的硬件架构,通过两次或三次牛顿-拉夫森迭代来计算往复,分别获得IEEE 754单精度和双精度标准的精度。我们用一个特别设计的二阶多项式近似倒数来估计初始值。通过使用二阶多项式,我们成功地在多项式近似计算和牛顿-拉夫森迭代中使用一个单一的硬件架构。因此,我们得到了一个最紧凑的硬件实现完整的互反计算。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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