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2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications最新文献

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Low Frequency Test for RF MEMS Switches 射频MEMS开关的低频测试
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.16
G. Rehder, S. Mir, L. Rufer, E. Simeu, Hoang Nam Nguyen
{"title":"Low Frequency Test for RF MEMS Switches","authors":"G. Rehder, S. Mir, L. Rufer, E. Simeu, Hoang Nam Nguyen","doi":"10.1109/DELTA.2010.16","DOIUrl":"https://doi.org/10.1109/DELTA.2010.16","url":null,"abstract":"In order to envision fault-tolerant SiPs and SoCs containing RF MEMS switches, this paper studies easily embedded low frequency tests for capacitive switches. The correlation between high frequency (S parameters) and low frequency (envelope of the high frequency signal) responses of a capacitive RF MEMS switch is analysed. This has been done by modeling both the electromechanical and RF behaviours of the switch and by a statistical simulation of the switch with Monte Carlo method. Next, it has been possible to predict the insertion loss, return loss and isolation of the switch from the low frequency measurements for a broad frequency range. Furthermore, by using the obtained correlations for two different frequencies, it was possible to recreate the S-parameters for the entire frequency spectrum with good agreement.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128055973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
16-QAM Transmitter and Receiver Design Based on FPGA 基于FPGA的16-QAM收发器设计
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.34
T. Vu, N. Duc, T. A. Vu
{"title":"16-QAM Transmitter and Receiver Design Based on FPGA","authors":"T. Vu, N. Duc, T. A. Vu","doi":"10.1109/DELTA.2010.34","DOIUrl":"https://doi.org/10.1109/DELTA.2010.34","url":null,"abstract":"The FPGA technology has been playing a considerable role in portable and mobile communication. This is due to the features of flexibility, accuracy and configurability in designing and implementation. The paper presents a complete design for a 16-QAM transmitter and receiver based on the Virtex4 FPGA Kit. The implemented system can be applied in particle. Based on the principles of carrier synchronization, time synchronization, core tools for phase-different detecting as well as adaptive equalization processing in System Generator (a software of Xilinx), the authors have designed a complete baseband IF 16-QAM system, in which the baseband signal is upconverted into IF frequency (up to 12MHz) at the transmitter and then is downconverted at the receiver. After timing synchronizing, the adaptive equalizing and phase recovering, the received baseband signal is displayed in the oscilloscope’s screen. These accurate experiments conducted in Virtex 4 FPGA board kit have shown a promising foundation for developing coding, algorithms in 16-QAM modulation scheme.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"17 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131276347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Design, Fabrication and Characterization of Asymmetric Fabry-Perot Modulator for Large Size Optical Shutter 大尺寸光学快门非对称法布里-珀罗调制器的设计、制造与特性研究
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.27
B. H. Na, Kwang-Mo Park, R. Sooraj, B. Jeong, Y. Song, Y. T. Lee, Chang-Soo Park
{"title":"Design, Fabrication and Characterization of Asymmetric Fabry-Perot Modulator for Large Size Optical Shutter","authors":"B. H. Na, Kwang-Mo Park, R. Sooraj, B. Jeong, Y. Song, Y. T. Lee, Chang-Soo Park","doi":"10.1109/DELTA.2010.27","DOIUrl":"https://doi.org/10.1109/DELTA.2010.27","url":null,"abstract":"We report the growth, fabrication and characterization of asymmetric Fabry-Perot modulators which function as optical shutter which can be used in 3-D imaging. By choosing appropriate electrode geometry, a reduction in parasitic capacitance was achieved. The results reveal that such devices are promising candidates as optical shutter for 3-D imaging applications.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116985930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The Discrimination of Metallic Coins Using a Scan Type Magnetic Camera 扫描式磁相机对金属硬币的鉴别
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.19
Jongwoo Jun, Jinyi Lee, Jaesun Lee
{"title":"The Discrimination of Metallic Coins Using a Scan Type Magnetic Camera","authors":"Jongwoo Jun, Jinyi Lee, Jaesun Lee","doi":"10.1109/DELTA.2010.19","DOIUrl":"https://doi.org/10.1109/DELTA.2010.19","url":null,"abstract":"Coins from different countries having similar sizes and weights could be used in a crime because they may have a large difference in economic value. An algorithm, which can be used to discriminate these coins, employs a scanning magnetic camera, which uses a linearly integrated 64 InSb Hall sensor array (LIHaS) on a NiZn ferrite wafer and a complex induced current-magnetic flux leakage method (CIC-MFL). The coins consist of paramagnetic metals or magnetically combined metals. The distribution of the magnetic field around each coin was measured at a lift-off of 1mm, and processed by using the #&240;VRMS/#&240;x term. It is possible to apply the peak-distances and the integrated absolute minimum values of #&240;VRMS/#&240;x in order to discriminate the coins. 170 cases that used 85 coins of 43 different denominations from 10 countries were examined to verify the proposed algorithm. The discrimination probability was 90.7 %.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115680706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High-speed 32-bit Signed/Unsigned Pipelined Multiplier 高速32位有符号/无符号流水线乘法器
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.10
Qingzheng Li, Guixuan Liang, A. Bermak
{"title":"A High-speed 32-bit Signed/Unsigned Pipelined Multiplier","authors":"Qingzheng Li, Guixuan Liang, A. Bermak","doi":"10.1109/DELTA.2010.10","DOIUrl":"https://doi.org/10.1109/DELTA.2010.10","url":null,"abstract":"In this paper, a novel unified implementation of signed/unsigned multiplication is proposed using a simple sign-control unit together with a line of multiplexers. The proposed approach is demonstrated through a 0.18um CMOS implementation of a 32-bit signed/unsigned multiplier. Reported results show that the proposed unified signed/unsigned implementation is very compact with only 0.45% silicon area overhead. The critical path delay of the proposed multiplier is about 3.13ns.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117207805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing 错误概率估计及其在带检查点的回滚恢复优化中的应用
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.25
Dimitar Nikolov, Urban Ingelsson, Virendra Singh, E. Larsson
{"title":"Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing","authors":"Dimitar Nikolov, Urban Ingelsson, Virendra Singh, E. Larsson","doi":"10.1109/DELTA.2010.25","DOIUrl":"https://doi.org/10.1109/DELTA.2010.25","url":null,"abstract":"The probability for errors to occur in electronic systems is not known in advance, but depends on many factors including influence from the environment where the system operates. In this paper, it is demonstrated that inaccurate estimates of the error probability lead to loss of performance in a well known fault tolerance technique, Roll-back Recovery with checkpointing (RRC). To regain the lost performance, a method for estimating the error probability along with an adjustment technique are proposed. Using a simulator tool that has been developed to enable experimentation, the proposed method is evaluated and the results show that the proposed method provides useful estimates of the error probability leading to near-optimal performance of the RRC fault-tolerant technique.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121255998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Nanomanipulation of Living Cells on a Chip Using Electric Field: General Concepts and Microdevices 利用电场对芯片上的活细胞进行纳米操作:一般概念和微器件
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.26
J. Villemejane, G. Mottet, O. Français, B. Pioufle, J. Lefevre, M. Woytasik, E. Dufour-Gergam, L. Mir
{"title":"Nanomanipulation of Living Cells on a Chip Using Electric Field: General Concepts and Microdevices","authors":"J. Villemejane, G. Mottet, O. Français, B. Pioufle, J. Lefevre, M. Woytasik, E. Dufour-Gergam, L. Mir","doi":"10.1109/DELTA.2010.26","DOIUrl":"https://doi.org/10.1109/DELTA.2010.26","url":null,"abstract":"Direct continuous (DC), pulsed (PEF) or alternative (AC) electric fields are well-known to induce specific effects on living cells or on molecules (including DNA and proteins) and are commonly used in molecular or cellular biology, and more recently for clinical treatment. Pharmacological industries and medical research are interesting in the development of new tools permitting to understand biophysical or biochemical phenomena involved in some diseases. They will permit to analyze more precisely protein pathways, to treat a large number of cells or to perform a complete reaction or process with the same device. Miniaturization is the best way to achieve these goals by integrating a lot of functions on the same substrate and by using the capabilities to parallelize some process.Here are presented recent results on active handling and treatment of cells in a microfluidic device. In particular we present recent achievements concerning cell fusion and electronanomanipulation.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127049263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic 一种基于5值逻辑的快速阈值测试生成算法
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.52
Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, H. Ichihara
{"title":"A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic","authors":"Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, H. Ichihara","doi":"10.1109/DELTA.2010.52","DOIUrl":"https://doi.org/10.1109/DELTA.2010.52","url":null,"abstract":"Threshold testing, which is a VLSI testing method based on the acceptability of faults, is effective in yield enhancement of VLSIs and in selectively hardening VLSI systems. A test generation algorithm for generating test patterns for unacceptable faults has been proposed, which is based on the 16-valued logic system. In this paper, we propose a fast test generation algorithm based on the 5-valued logic system. Experimental results show that our proposed algorithm can generate test patterns for unacceptable faults with small computational time, compared with that based on the 16-valued logic system.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130316970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits 扫描路径电路扩展故障类的快速故障仿真
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.32
R. Ubar, S. Devadze, J. Raik, A. Jutman
{"title":"Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits","authors":"R. Ubar, S. Devadze, J. Raik, A. Jutman","doi":"10.1109/DELTA.2010.32","DOIUrl":"https://doi.org/10.1109/DELTA.2010.32","url":null,"abstract":"In this paper, a new very fast fault simulation method for extended class of faults is proposed. The method is based on a two-phase procedure. In the first phase, a novel parallel exact critical path fault tracing is used to determine all the \"active\" nodes with detectable stuck-at faults. In the second phase of the procedure, reasoning is carried out to determine the detectable physical defects based on the information about the \"active\" nodes and the current (or previous) logic state of the network.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"402 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131842932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Designing a Harware Accelerator for Face Recognition Using Vector Quantization and Principal Component Analysis as a Component of SoPC 基于矢量量化和主成分分析的人脸识别硬件加速器设计
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.56
Diem Tran, Thi To, T. Huynh, Phuong Nguyen
{"title":"Designing a Harware Accelerator for Face Recognition Using Vector Quantization and Principal Component Analysis as a Component of SoPC","authors":"Diem Tran, Thi To, T. Huynh, Phuong Nguyen","doi":"10.1109/DELTA.2010.56","DOIUrl":"https://doi.org/10.1109/DELTA.2010.56","url":null,"abstract":"A flexible hardware accelerator for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real- time image compression and recognition applications. In the system, the number of elements for each codeword and the number of codewords in the system can be changed easily for different applications with the use of an embedded CPU. The architecture allows using look up tables (LUTs), single-instruction multiple data (SIMD) and two-stage pipeline architecture. This leads to high speed operation suitable for real-time applications. On the other hand, over the last ten years or so, face recognition has become a popular area of research in computer vision and one of the most successful applications of image analysis and understanding. A number of statistical analysis methods have showed their efficiencies in recognition applications. Thus, in this research, an improved method for face recognition using principal component analysis (PCA) and vector quantization (VQ) have been developed as a component of SoPC using a DSP FPGA Development Kit, Stratix II Edition from Altera.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131314406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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