高速32位有符号/无符号流水线乘法器

2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI:10.1109/DELTA.2010.10

Qingzheng Li, Guixuan Liang, A. Bermak

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引用次数: 22

摘要

本文提出了一种新的有符号/无符号乘法的统一实现方法，该方法使用一个简单的符号控制单元和一组多路复用器。通过0.18um CMOS实现的32位有符号/无符号乘法器演示了所提出的方法。报告的结果表明，提出的统一的有符号/无符号实现非常紧凑，只有0.45%的硅面积开销。该倍增器的关键路径延迟约为3.13ns。

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A High-speed 32-bit Signed/Unsigned Pipelined Multiplier

In this paper, a novel unified implementation of signed/unsigned multiplication is proposed using a simple sign-control unit together with a line of multiplexers. The proposed approach is demonstrated through a 0.18um CMOS implementation of a 32-bit signed/unsigned multiplier. Reported results show that the proposed unified signed/unsigned implementation is very compact with only 0.45% silicon area overhead. The critical path delay of the proposed multiplier is about 3.13ns.

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来源期刊

2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications

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