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2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications最新文献

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Read-out Circuit Analysis for High-speed Low-noise VCO Based APS CMOS Image Sensor 基于VCO的高速低噪声APS CMOS图像传感器读出电路分析
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.11
Fang Tang, A. Bermak
{"title":"Read-out Circuit Analysis for High-speed Low-noise VCO Based APS CMOS Image Sensor","authors":"Fang Tang, A. Bermak","doi":"10.1109/DELTA.2010.11","DOIUrl":"https://doi.org/10.1109/DELTA.2010.11","url":null,"abstract":"A detailed read-out circuit analysis of the VCO based APS CMOS image sensor is presented in this paper. According to the mathematic analysis and simulation results, the read-out speed should be decreased when reducing the bias current. Moreover, the feature of the device gain factor and the source follower's threshold voltage are vestigated, showing important effects with respect to not only the read-out time but also the energy consumption. The proposed VCO based read-out circuit and frequency counter consist an equivalent bandpass filter. According to the transfer function analysis of this equivalent filter, the noise cancellation efficiency is jointly determined by the bias current, device gain factor and source follower's threshold voltage, which constitute the basic principles for high-speed low-noise CMOS APS image sensor design.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114943269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Adaptive Huffman Decoding Algorithm for MP3 Decoder MP3解码器的自适应霍夫曼解码算法
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.22
Hoang-Anh Pham, Van-Hieu Bui, Anh-Vu Dinh-Duc
{"title":"An Adaptive Huffman Decoding Algorithm for MP3 Decoder","authors":"Hoang-Anh Pham, Van-Hieu Bui, Anh-Vu Dinh-Duc","doi":"10.1109/DELTA.2010.22","DOIUrl":"https://doi.org/10.1109/DELTA.2010.22","url":null,"abstract":"This paper proposes a novel array data structure to represent Huffman code table and an adaptive algorithm for Huffman decoding based on Single-side Growing Huffman Coding approach which provides a memory efficient and high-speed decoding algorithm. The search time of the proposed algorithm for finding a symbol is the ceiling of (CL/4) where CL is the code length of the corresponding symbol. The implementation of the proposed algorithm is applied for MP3 decoding and the experimental result shows that our algorithm is applicable to all Huffman decoding applications.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115329684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial 基于忆阻器的横条数字逻辑实现-教程
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.70
T. Raja, S. Mourad
{"title":"Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial","authors":"T. Raja, S. Mourad","doi":"10.1109/DELTA.2010.70","DOIUrl":"https://doi.org/10.1109/DELTA.2010.70","url":null,"abstract":"A memristor is a passive electronic device that was proposed and described by Leon Chua in 1971. The first practical implementation has been realized by Stan Williams’ group at HP Labs in 2008. The goal of this paper is to give the reader a brief introduction to the possibilities of logic design using memristors. It paper is intended as a tutorial on how to use memristor crossbars for logic design and is a consolidation of various recent publications.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120860653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
A Novel Design Framework for Business Process Modelling in Automotive Industry 汽车行业业务流程建模的新设计框架
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.48
Zwikamu Dubani, B. Soh, C. Seeling
{"title":"A Novel Design Framework for Business Process Modelling in Automotive Industry","authors":"Zwikamu Dubani, B. Soh, C. Seeling","doi":"10.1109/DELTA.2010.48","DOIUrl":"https://doi.org/10.1109/DELTA.2010.48","url":null,"abstract":"The Business Process Modeling Notation (BPMN) was developed by an international body called the Business Process Management Initiative (BPMI). The strengths of BPMN include that it is easily readable and understandable, and could be transformed into the current widely used business process implementation language, the Business Process Execution Language (BPEL). However, there are some fundamental incompatibilities between BPMN and BPEL, which make it difficult to generate BPEL code for implementation from BPMN models.The aim of this paper is to investigate the synergic uses of BPMN and BPEL to model and implement executable business processes. To that end, we propose a Business Process Modelling framework. Then we apply it to a real life business process scenario involving a typical manufacturing process in the automotive industry. From the case study, we are able to conclude that BPMN is suitable for modelling business processes and then implementing the model in BPEL in spite of the incompatibilities between the former and the latter.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124048917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties 生成具有全输出-传播特性的紧迁移测试的伪布尔技术
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.58
T. Iwagaki, M. Kaneko
{"title":"A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties","authors":"T. Iwagaki, M. Kaneko","doi":"10.1109/DELTA.2010.58","DOIUrl":"https://doi.org/10.1109/DELTA.2010.58","url":null,"abstract":"This paper presents a technique for deriving a test set that detects each transition fault at all the reachable outputs from the fault site. It is known that such tests, which are called all-output-propagation (AOP) ones, can enhance the detectability of un-modeled defects. In order to generate compact AOP tests, pseudo-Boolean (0-1 integer programming) model is introduced in this paper. Moreover, a simple and reasonable heuristic way is also introduced to reduce the size of AOP tests efficiently.It is shown that the proposed method can generate compact AOP tests in a reasonable amount of test generation time through some experiments.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132209756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CPU Testability in Embedded Systems 嵌入式系统中的CPU可测试性
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.33
J. Sosnowski, Lukasz Tupaj
{"title":"CPU Testability in Embedded Systems","authors":"J. Sosnowski, Lukasz Tupaj","doi":"10.1109/DELTA.2010.33","DOIUrl":"https://doi.org/10.1109/DELTA.2010.33","url":null,"abstract":"The paper deals with the problem of testing CPUs in embedded systems taking into account application properties. Basing on the developed original software tools we have analysed the coverage of CPU functionality and operational stresses for many benchmark programs. The experimental results confirmed the need of introducing application driven testing of CPUs to assure high fault coverage with acceptable software and time overheads. This original approach has been used in some real systems.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133531421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Hybrid CMOS DPS with Conditional Data Readout Scheme 一种具有条件数据读出方案的混合CMOS DPS
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.64
K. Lau, S. Léomant, A. Bermak
{"title":"A Hybrid CMOS DPS with Conditional Data Readout Scheme","authors":"K. Lau, S. Léomant, A. Bermak","doi":"10.1109/DELTA.2010.64","DOIUrl":"https://doi.org/10.1109/DELTA.2010.64","url":null,"abstract":"In this paper, a hybrid CMOS pulse width modulation (PWM) digital pixel sensor (DPS) is proposed. In order to reduce the pixel area, the proposed architecture requires only a two bit on-pixel memory while placing the remaining six bits outside the array, assuming a common resolution of eight bits. This new architecture reduces the size of the pixel significantly as the memory requirement at pixel level is divided by 4. The eight bit resolution is maintained by scanning the array of pixels periodically during the integration period. In addition, a conditional data readout scheme is proposed in order to reduce the unnecessary read operations of pixel-level memories. Therefore, switching activity of data buses and dynamic power are kept under control. In our implementation, the pixel contains only 21 transistors and occupies an area of about 9μm x 9μm, with a fill factor of 12% using a 0.18μm CMOS process. Simulation results show a 50% reduction of read bit-lines switching activity at low illumination conditions, using our conditional readout scheme.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116277848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers 对差分功率分析的阻力评估:设计人员的执行时间优化
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.50
G. D. Natale, M. Flottes, B. Rouzeyre
{"title":"Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers","authors":"G. D. Natale, M. Flottes, B. Rouzeyre","doi":"10.1109/DELTA.2010.50","DOIUrl":"https://doi.org/10.1109/DELTA.2010.50","url":null,"abstract":"This paper proposes a novel method intended to accelerate the checking of the robustness of a device against Differential Power Analysis. We propose an algorithm for the automatic selection of shortest short input vector sequence that leads to the secret key breakthrough. We show that the selected sequence remains valid for different designs of the same cryptographic function.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"374 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116625092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy-aware Filter Cache Architecture for Multicore Processors 多核处理器的能量感知过滤器缓存架构
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.21
Young Jin Park, H. Choi, C. Kim, Jong-Myon Kim
{"title":"Energy-aware Filter Cache Architecture for Multicore Processors","authors":"Young Jin Park, H. Choi, C. Kim, Jong-Myon Kim","doi":"10.1109/DELTA.2010.21","DOIUrl":"https://doi.org/10.1109/DELTA.2010.21","url":null,"abstract":"Energy consumption as well as performance should be considered when designing high-performance multicore processors. The energy consumed in the instruction cache accounts for a significant portion of total processor energy consumption. Therefore, energy-aware instruction cache design techniques are essential for high-performance multicore processors. In this paper, we propose new instruction cache architecture, which is based on the level-0 cache composed of filter cache and victim cache together, for multicore processors. The proposed architecture reduces the energy consumption in the instruction cache by reducing the number of accesses to the level-1 instruction cache. We evaluate the proposed design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed technique reduces the energy consumption in the instruction cache by up to 3.4% compared to the conventional filter cache architecture. Moreover, the proposed architecture shows better performance over the conventional filter cache architecture.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125025766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An Event-Assisted Sequencer to Accelerate Matrix Algorithms 一种加速矩阵算法的事件辅助排序器
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications Pub Date : 2010-01-13 DOI: 10.1109/DELTA.2010.12
A. Burdeniuk, K. To, C. Lim, M. Liebelt
{"title":"An Event-Assisted Sequencer to Accelerate Matrix Algorithms","authors":"A. Burdeniuk, K. To, C. Lim, M. Liebelt","doi":"10.1109/DELTA.2010.12","DOIUrl":"https://doi.org/10.1109/DELTA.2010.12","url":null,"abstract":"This paper presents a sequencer that accelerates matrix algorithms arising naturally in many multimedia and signal processing applications. The accelerator has been designed to carry out data management tasks common to these algorithms. A novel event-based parameter update mechanism allows production of continuously varying patterns to access triangular, banded and other irregular matrix structures. It has been verified that the accelerator significantly reduces the workload of the attached CPU for a wide range of algorithms. The accelerator has been implemented on a Virtex-5 FPGA platform where it required 1856 slices and achieved a post place-and-route speed of 64 MHz.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133531657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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