Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, H. Ichihara
{"title":"A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic","authors":"Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, H. Ichihara","doi":"10.1109/DELTA.2010.52","DOIUrl":null,"url":null,"abstract":"Threshold testing, which is a VLSI testing method based on the acceptability of faults, is effective in yield enhancement of VLSIs and in selectively hardening VLSI systems. A test generation algorithm for generating test patterns for unacceptable faults has been proposed, which is based on the 16-valued logic system. In this paper, we propose a fast test generation algorithm based on the 5-valued logic system. Experimental results show that our proposed algorithm can generate test patterns for unacceptable faults with small computational time, compared with that based on the 16-valued logic system.","PeriodicalId":421336,"journal":{"name":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DELTA.2010.52","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
Threshold testing, which is a VLSI testing method based on the acceptability of faults, is effective in yield enhancement of VLSIs and in selectively hardening VLSI systems. A test generation algorithm for generating test patterns for unacceptable faults has been proposed, which is based on the 16-valued logic system. In this paper, we propose a fast test generation algorithm based on the 5-valued logic system. Experimental results show that our proposed algorithm can generate test patterns for unacceptable faults with small computational time, compared with that based on the 16-valued logic system.