A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic

Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, H. Ichihara
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引用次数: 7

Abstract

Threshold testing, which is a VLSI testing method based on the acceptability of faults, is effective in yield enhancement of VLSIs and in selectively hardening VLSI systems. A test generation algorithm for generating test patterns for unacceptable faults has been proposed, which is based on the 16-valued logic system. In this paper, we propose a fast test generation algorithm based on the 5-valued logic system. Experimental results show that our proposed algorithm can generate test patterns for unacceptable faults with small computational time, compared with that based on the 16-valued logic system.
一种基于5值逻辑的快速阈值测试生成算法
阈值测试是一种基于故障可接受性的超大规模集成电路测试方法,是提高超大规模集成电路成品率和选择性硬化超大规模集成电路系统的有效方法。提出了一种基于16值逻辑系统的可接受故障测试模式生成算法。本文提出了一种基于5值逻辑系统的快速测试生成算法。实验结果表明,与基于16值逻辑系统的测试模式相比,该算法可以在较小的计算时间内生成可接受故障的测试模式。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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