VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects最新文献

{"title":"Prospective current mode approach for on-chip interconnects in integrated circuit designs","authors":"Yash Agrawal, R. Chandel, Mekala Girish Kumar, R. Parekh","doi":"10.1049/pbcs073g_ch9","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch9","url":null,"abstract":"In today's sophisticated nanoera and miniaturised densely packed integrated circuit (IC) designs, on-chip interconnects have become one of the dominant governing factors in determining the overall performance of very large scale integration (VLSI) system. In pursuit to attain high performance, to quench the thirst of continuously increasing demands of semiconductor VLSI industry and to boost up the integrated applications on the calculated limited silicon chip area, hunt for new potential and prospective design techniques have always been on priority and rigorously explored by several researchers. Current mode approach for on-chip interconnects is one of the aptly suited signalling schemes and effective performance improvement techniques for high-end IC designs. An accurate analytical model formulation of on-chip interconnects together with prospective current mode signalling (CMS) scheme and evaluating their performance are crucial and important issue. In this chapter, explicit expressions of various performance metrics for on-chip interconnects are formulated. The performance of interconnects using two varying signalling schemes namely conventional voltage and advanced current mode is investigated. The various performance metrics considered are voltage swing over interconnect line, delay, power dissipation, energy dissipation and bandwidth. It is found that voltage mode signalling (VMS) has advantage of reduced power and energy dissipation of nearly 8.6% and 9.2%, respectively, as compared to CMS scheme. It is also investigated that CMS has about 53% lesser delay and 161% higher bandwidth than VMS scheme. The effect of interconnect length and pulse period variations on the performance parameters of the interconnect using VMS and CMS schemes are also analysed. The proposed analytical model results are validated using SPICE simulation EDA tool and high level of accuracy has been realised. The present work keenly focuses on advanced current mode approach and henceforth analysing the effectiveness of different signalling schemes for high performance on-chip VLSI interconnects in ICs.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121804556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Back Matter","authors":"","doi":"10.1049/pbcs073g_bm","DOIUrl":"https://doi.org/10.1049/pbcs073g_bm","url":null,"abstract":"","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129802987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"UTB III–V-OI-Si MOS transistor: the future transistor for VLSI design","authors":"S. Maity, Soumya Pandit","doi":"10.1049/pbcs073g_ch2","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch2","url":null,"abstract":"In power-constrained very large scale integration (VLSI) design, the transistors need to operate with extremely scaled supply voltage ( 0.4-0.5 V) and must have good electrostatic integrity to minimize the static power dissipation. But these lead to compromise in switching speed. This competing requirement necessitates the introduction of new material to form the channel of a MOS transistor, in which the inversion charge carriers travel with much higher velocity than that in silicon. With this, the loss of switching speed can be reduced. III-V compound semiconductors such as GaAs, InGaAs and InAs have very good electron transport properties. The mobility of electrons in InGaAs or InAs is more than ten times higher than that for silicon at a comparable sheet charge density [1]. However, one intrinsic drawback of the MOS transistor made of III-V semiconductors is worse device electrostatic integrity. Therefore, ultrathin body (UTB) structures like UTB-on-insulator (UTBOI) structure, FinFET or trigate structure and nanowire field effect transistor (FET) structure with III-V-based channel material have gained attention of the semiconductor device researchers for applications in next generation VLSI circuits. It may be noted that any new technology is desired to be compatible with an Si-based CMOS platform for cost-effective mass production and system-on-chip applications. Direct wafer bonding (DWB) technique is an important approach to grow III-V-OI structures with thin buried oxide (BOX) layers on Si wafers. This chapter provides a comprehensive overview of a UTB III-V-OI-Si MOS transistor. The advantages of using III-V channel materials over Si are summarized using calibrated technology computer-aided design (TCAD) simulation results. Gate-source/drain (G-S/D) underlap technique is discussed as an approach to enhance electrostatic integrity. Finally, UTB, GaAs-OI structure is briefly introduced as a candidate for a p-channel MOS transistor.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131583227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of oxide thickness variation on the performance of junctionless FinFET","authors":"S. Kaundal, A. Rana","doi":"10.1049/pbcs073g_ch5","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch5","url":null,"abstract":"The relentless advances in the complementary metal oxide semiconductor (CMOS) technology have mainly enabled through dimensional downscaling of the transistor which brings out numerous challenges such as controlling short channel effects (SCEs), leakage current and fabrication complexity of forming high-quality metallurgical junction at sub-nanoscale regime. Junctionless (JL) concept in the transistor has emerged recently and shown tremendous potential for the future technology generation. It not only simplified the fabrication process but also provided the comparable performance to those of conventional junction-based metal oxide semiconductor (MOS) devices. This work, for the first time, demonstrates the impact of oxide thickness variation (OTV) on a 14 nm junctionless FinFET (JL FinFET) using extensive technology computer-aided design (TCAD) device simulation. Results show that the deviation in threshold voltage and OFF-current are seriously impacted by OTV for JL FinFET structure as compared to the normal inversion mode (IM) counterparts. Furthermore, the joint impact of all the intrinsic statistical variability sources including OTV, random dopant fluctuation (RDF) and gate work function variation (WFV) on threshold voltage has been investigated.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125144783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation framework for GaN devices with special mention to reliability concern","authors":"Sushanta Bordoloi, Ashok Ray, G. Trivedi","doi":"10.1049/pbcs073g_ch4","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch4","url":null,"abstract":"In this chapter, we will look into some of the reliability concern in first few sections and fi nally propose a simulation (numerical) framework along with model development to understand these effects.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127027692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"III–V compound semiconductor transistors–from planar to nanowire structures","authors":"D. Nirmal, J. Ajayan","doi":"10.1049/pbcs073g_ch1","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch1","url":null,"abstract":"In this chapter, many aspects of III-V semiconductor transistors were reviewed. The following topics was discussed: epitaxial growth techniques; heterostructure and quantum well; heterojunction bipolar transistors; high electron mobility transistors; quantum well MOSFETs; and nanowire field effect transistors.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115744804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of through silicon vias for improved performance in 3D IC applications","authors":"Vobulapuram Ramesh Kumar, S. J. Basha, Badugu Divya Madhuri, S. Sunithamani","doi":"10.1049/pbcs073g_ch10","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch10","url":null,"abstract":"This chapter discusses the design aspects of TSVs for 3D -IC applications. To improve the performance of TSVs, different insulating liners with low dielectric constants are used in place of the conventional insulating liner. Moreover, it has been noticed that the TSVs with copper filler material faces many problems such as skin effect, high resistance and electromigration effects. In order to overcome these problems and to improve the signal integrity, multiwalled carbon nanotubes (MWCNTs) are used that further improves the performance of TSVs. All the proposed structures are designed using the industry standard HSPICE simulator. The performance improvements in the proposed structures are verified by comparing the results with the conventional TSVs.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132389201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transient fault secured/tolerant architecture for DSP core","authors":"Deepak Kachave, A. Sengupta","doi":"10.1049/pbcs073g_ch16","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch16","url":null,"abstract":"In this chapter we have provided a detailed description to TFs, its origin and its impact on integrated circuits. Further, we have discussed recent state-of-the-art methodologies present in the literature that provides security and/or tolerance subsequent CS doesn't require shifting of primary outputs. Hence, overall schedule delay is not affected. Similarly, as shown in Figure 16.15, for k = 10 and k m = 4, a small increment in the delay for [4] in case of large size benchmarks is observed. However, the delay overhead is within acceptable limits. (Note: during above delay comparison the delay overhead of two CS due to comparators and voter is not considered for analysis of delay overhead. This was done to provide analysis of delay overhead resulting only due to shifting of operations during scheduling and allocation.)","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133036319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Methods to design ternary gates and adders","authors":"Y. Shrivastava, T. Gupta","doi":"10.1049/pbcs073g_ch14","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch14","url":null,"abstract":"This chapter contains various designs of ternary logic gates and adders using complementary metal oxide semiconductor transistors (CMOS) and carbon nanotube field effect transistors (CNTFETs). As the time goes by binary logic is getting harder to implement on smaller scale, so ternary logic becomes a better alternative of the same. Ternary logic has the simplicity over binary logic and it is energy efficient also. In today's world when it's a challenge to implement the circuit design on as small level as possible, binary logic is limited due to large number of interconnects and large chip area, which is reduced in ternary logic. In ternary logic, there is a requirement of the multithreshold transistors, which can switch on and switch off on the particular voltage level when the circuit demands, since CNTFET's threshold can be changed by varying their chirality or tube diameter they have become the most suitable devices to implement ternary logic. In this chapter various research works on ternary gates and adders will be discussed and a comparison between them will be made on various performance parameters such as power delay product (PDP), transistor count and time delay. These parameters are evaluated and compared by simulating these circuits.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115868228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Radiation hard circuit design: flip-flop and SRAM","authors":"G. Kaushal, S. Rathod, C. Raghuram, S. Dasgupta","doi":"10.1049/pbcs073g_ch12","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch12","url":null,"abstract":"As the transistor size scales down exponentially to nanometric dimensions, the susceptibility of electronic circuits to radiation increases drastically. Protection against the radiation is important in the field of biomedical, aerospace, communication and computing. Flip-flops (FFs) and static random access memories (SRAMs) are used to store the data in many critical applications where their performance must be resilient to radiation exposures to guarantee reliability. Therefore development of resilient FFs and SRAM are the challenging and demanding problems. In this chapter, different approaches are analysed to design these radiation hard circuits.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124755385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}