UTB III–V-OI-Si MOS transistor: the future transistor for VLSI design

In power-constrained very large scale integration (VLSI) design, the transistors need to operate with extremely scaled supply voltage ( 0.4-0.5 V) and must have good electrostatic integrity to minimize the static power dissipation. But these lead to compromise in switching speed. This competing requirement necessitates the introduction of new material to form the channel of a MOS transistor, in which the inversion charge carriers travel with much higher velocity than that in silicon. With this, the loss of switching speed can be reduced. III-V compound semiconductors such as GaAs, InGaAs and InAs have very good electron transport properties. The mobility of electrons in InGaAs or InAs is more than ten times higher than that for silicon at a comparable sheet charge density [1]. However, one intrinsic drawback of the MOS transistor made of III-V semiconductors is worse device electrostatic integrity. Therefore, ultrathin body (UTB) structures like UTB-on-insulator (UTBOI) structure, FinFET or trigate structure and nanowire field effect transistor (FET) structure with III-V-based channel material have gained attention of the semiconductor device researchers for applications in next generation VLSI circuits. It may be noted that any new technology is desired to be compatible with an Si-based CMOS platform for cost-effective mass production and system-on-chip applications. Direct wafer bonding (DWB) technique is an important approach to grow III-V-OI structures with thin buried oxide (BOX) layers on Si wafers. This chapter provides a comprehensive overview of a UTB III-V-OI-Si MOS transistor. The advantages of using III-V channel materials over Si are summarized using calibrated technology computer-aided design (TCAD) simulation results. Gate-source/drain (G-S/D) underlap technique is discussed as an approach to enhance electrostatic integrity. Finally, UTB, GaAs-OI structure is briefly introduced as a candidate for a p-channel MOS transistor.