VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects最新文献_第2页

Design and analysis of variability aware FinFET-based SRAM circuit design 基于finfet的可变感知SRAM电路设计与分析

VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects Pub Date : 2019-09-27 DOI: 10.1049/pbcs073g_ch6

D. Nayak, Debiprasad Priyabrata Achary, P. Rout, U. Nanda

{"title":"Design and analysis of variability aware FinFET-based SRAM circuit design","authors":"D. Nayak, Debiprasad Priyabrata Achary, P. Rout, U. Nanda","doi":"10.1049/pbcs073g_ch6","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch6","url":null,"abstract":"In modern SOC design SRAM has become an integral part owing to its capability to form a bridge and overcome the speed mismatch problem between the high speed processor and the low speed data storage devices. Because of the read and write operation of SRAM cell having conflicting transistor sizing requirement, it is very difficult to maintain the transistor size to satisfy both the needs. The destructive nature of read operation enforces a serious thought about SRAM cell data stability. Transistor sizing and cell stability already being a critical problem becomes even more critical when we consider the process and temperature variation. Thus the SRAM should be designed with keeping the process and temperature variation in mind. The random fluctuation in device parameters such as transistor width, length, oxide thickness, oxide capacitance and doping concentration leads to variation in the threshold voltage and other transistor characteristics. The change in these transistor characteristics alters the SRAM cell performance. Hence this should also be taken care of to ensure the cell performance to be in the desired range even in presence of random fluctuation during fabrication process. The various performance measure such as SNM, write SNM, speed and power consumption must be tested under worst process corner as well over a wide temperature range to ensure that they lie in the acceptable range during worst operating condition. Also these parameters must be tested using Monte Carlo simulation to ensure a robust operation in presence of random fluctuation during fabrication process.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128716373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Phase change memory: electrical circuit modelling, nanocrossbar performance analysis and applications 相变存储器:电路建模、纳米横棒性能分析及应用

VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects Pub Date : 2019-09-27 DOI: 10.1049/pbcs073g_ch13

N. El-Hassan, T. N. Kumar, H. Almurib

{"title":"Phase change memory: electrical circuit modelling, nanocrossbar performance analysis and applications","authors":"N. El-Hassan, T. N. Kumar, H. Almurib","doi":"10.1049/pbcs073g_ch13","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch13","url":null,"abstract":"Phase change memory (PCM) functions by thermally induced phase change of chalcogenide material, typically from disordered highly resistive amorphous phase with short range atomic order and low free electron density, to a low resistance crystalline phase with long range atomic order and high free electron density, or vice versa [1,2]. PCM is one of the potential emerging nonvolatile memory (NVM) technologies to replace flash memory and be the technology for storage class memory due to its desirable properties such as short access time, long data retention, high endurance, scalability, CMOS compatibility and multibit storage [3-8]. Hence it is time to have an accurate electrical model of the PCM in order to realise a straightforward and timely implementation of PCM in an integrated circuit. This chapter presents the electrical circuit model of multibit PCM cell that accurately simulates the temperature profile, the crystalline fraction and the resistance of the cell as a function of the programming pulse. Also, the precise modelling of the drift phenomenon of resistance and threshold voltage at the amorphous phase is presented. The presented model's I-V characteristics are correlated with experimental data to demonstrate the validity of the developed PCM model. Next this chapter presents the analysis of PCM cells on a nanocrossbar as a memory system. The effect of connecting wires resistance in the performance of the PCM array structure, the amount of energy lost across each PCM cell and programmed state of the PCM cell is also discussed. It has been shown that the energy consumed in connecting wires decreases the power supplied to PCM cells thus resulting in higher programmed low resistive state (Rcrystalline). Additionally, methods to mitigate the programmedRcrystalline reliability issue are discussed in detail. Finally, the chapter concludes with the discussion on PCM-based memory application in implementing a logic function using the look-up-table (LUT), that is, PCM-based LUTs.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"5 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129306329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modelling interconnects for future VLSI circuit applications 建模互连为未来的VLSI电路应用

VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects Pub Date : 2019-09-27 DOI: 10.1049/pbcs073g_ch7

Manodipan Sahoo

引用次数: 0

Nanomagnetic computing for next generation interconnects and logic design 用于下一代互连和逻辑设计的纳米磁计算

VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects Pub Date : 2019-09-27 DOI: 10.1049/pbcs073g_ch8

Sanghamitra Debroy, Santhosh Sivasubramani, S. G. Acharyya, A. Acharyya

引用次数: 3

Assessment of SiGe/Si heterojunction tunnel field-effect transistor for digital VLSI circuit applications 数字VLSI电路中SiGe/Si异质结隧道场效应晶体管的评估

VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects Pub Date : 2019-09-27 DOI: 10.1049/pbcs073g_ch3

S. Pandey, P. Kondekar, Anju, K. Nigam, D. Sharma

{"title":"Assessment of SiGe/Si heterojunction tunnel field-effect transistor for digital VLSI circuit applications","authors":"S. Pandey, P. Kondekar, Anju, K. Nigam, D. Sharma","doi":"10.1049/pbcs073g_ch3","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch3","url":null,"abstract":"In this chapter, we report p+-n+-i-n+ (n -type) and n+-p+-i-p+ (p -type) SiGe/Si hetero double gate tunnel field-effect transistor (TFET) (H-DGTFET) for low power circuit applications. To achieve the optimum performance of the above devices, the Silicon (Si) and Germanium (Ge) composition of 30% and 70% (SiO3 Ge0.7), respectively, considered in source region, and a heavily doped (HD) layer placed in the channel near the source-channel junction are employed. Due to lower tunnel resistance offered by SiGe, the technology computer aided design (TCAD) device simulations of both the configurations show superior results in terms of DC and analog/radio frequency (RF) parameters as compared to the conventional TFETs. However, linearity of n-type device is analyzed in terms of VIP2, VIP3, and PldB. Furthermore, the circuit-level performance assessment is done by implementing complementary primary digital circuits (such as an inverter, NAND, and NOR logics) using lookup table-based Verilog-A model of the H-DGTFET. Comparison table shows impressive results in terms of digital performance parameters such as static noise margin (SNM), noise margin high (NMH ), noise margin low (NML ), high-to -low delay (τphl ), low-to-high delay (τphl,), and propagation delay (τp) as compared to the recently reported work","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131206107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Single EXCCII based square/triangular wave generator for capacitive sensor interfacing and brief review 电容式传感器接口中基于EXCCII的单方波/三角波发生器及简要综述

VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects Pub Date : 2019-09-27 DOI: 10.1049/pbcs073g_ch15

B. Chaturvedi, Atul Kumar

{"title":"Single EXCCII based square/triangular wave generator for capacitive sensor interfacing and brief review","authors":"B. Chaturvedi, Atul Kumar","doi":"10.1049/pbcs073g_ch15","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch15","url":null,"abstract":"Square/triangular wave generators are very important building blocks and find wide applications in resistive/capacitive sensor interfaces, pulse width modulation (PWM), analogue to digital convertor and so on. A variety of generator circuits have been reported in the literature so far. This chapter gives a brief review of existing generator circuits. To further enrich the area, this chapter proposes a novel square/triangular wave generator circuit, which is realised using single extra-X second generation current conveyor (EXCCII), four resistors and one grounded capacitor. The circuit provides both square wave and triangular wave in voltage-mode simultaneously. The circuit can operate at the frequency as low as 100 mHz and is capable of providing a wide sweep range of frequency of six decades (100 mHz to 310 kHz). The proposed generator can precisely detect the capacitor variations up to six decades in the range of 100 pF to 100 mF. Therefore, the proposed circuit finds suitable application as capacitive sensor interface with low-voltage and low-power characteristics. The effects of nonidealities and parasitic of EXCCII along with the effects of temperature variations on the proposed generator circuit are studied. The possible aspect of adjusting the duty cycle of output waveforms via DC current source is also shown. The theoretical proposal has been verified by SPICE simulations.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114966493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Prospective graphene-based through silicon vias in three-dimensional integrated circuits 三维集成电路中基于石墨烯的硅通孔的前景

VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects Pub Date : 2019-09-27 DOI: 10.1049/pbcs073g_ch11

Mekala Girish Kumar, R. Dhiman, Yash Agrawal, A. Chandel

{"title":"Prospective graphene-based through silicon vias in three-dimensional integrated circuits","authors":"Mekala Girish Kumar, R. Dhiman, Yash Agrawal, A. Chandel","doi":"10.1049/pbcs073g_ch11","DOIUrl":"https://doi.org/10.1049/pbcs073g_ch11","url":null,"abstract":"The package of the silicon chip is an important aspect of VLSI. The package determines the size of ICs. Different IC packages allow the dies to connect with the PCB and it affects the performance of IC. These packages offer a connection with PCB, atmosphere protection and mechanical stability for the IC. The demand of improvement in IC package is increasing day by day due to the increased density of IC. The design of packages grew from through-hole to surface mount technology, from WB to flip -chip and from dual-inline packaging to chip scale packaging. Although there has been tremendous progress in this area, it is in the middle of another evolution. This progress is the evaluation of the 3D packaging design. This design provides more than 100% PE and enhances performance metrics through decreased interconnection length. This is achieved by vertical connections of stacking chips using TSVs. Vertically connected TSVs also facilitate heterogeneous integration of dies in realising on a single chip. However, the selection of filler material in TSVs plays a vital role in the reliability of 3D ICs. There are some challenges in the areas of thermal management and electrical design. In the present study, four different surrounding materials, that is, SiO2 , Si3N4 , Al203 and Hf0 2 have been considered. The equivalent stress and the resultant structure deformation of filler material (Cu and CNT) of TSVs are observed. It is noticed that the deformation in the structure of CNT-based TSVs is lesser as compared to Cu -based TSVs. Further, Hf0 2 possesses significantly lesser deformation as compared to SiO2 and Al2O3.","PeriodicalId":417544,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 2: Devices, circuits and interconnects","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128539844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0