Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545)最新文献_第3页

Electric and thermal transient effects in high power optical devices 高功率光学器件中的电和热瞬态效应

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291320

G. Farkas, S. Haque, F. Wall, P. S. Martin, A. Poppe, Q. van Voorst Vader, G. Bognár

引用次数: 60

Noise and cooling in electronics packages 电子封装中的噪音和冷却

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291318

R. Lyon, A. Bergles

引用次数: 17

New correlations between electrical current and temperature rise in PCB traces PCB走线中电流和温升之间的新相关性

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291337

Johannes Adam Flomerics, Germany johannes. adam

{"title":"New correlations between electrical current and temperature rise in PCB traces","authors":"Johannes Adam Flomerics, Germany johannes. adam","doi":"10.1109/STHERM.2004.1291337","DOIUrl":"https://doi.org/10.1109/STHERM.2004.1291337","url":null,"abstract":"The widely used design rule IPC-2221 (=MIL-STD-275) for the 'current carrying capacity' of traces on printed circuit boards is subject of a closer investigation. These historical studies on correlations between electrical current and temperature rise of the trace can be reproduced by numerical heat transfer simulations only if the board has a back 35/spl mu/m copper layer and the thickness of the trace is 35 /spl mu/m. As this makes an. extrapolation to other boards impossible, we will present numerical studies for FR4-based board models with other copper planes and also for ceramic substrates. For a better understanding of the results, 2D heat conduction calculations for traces on boards with constant internal and external conditions are performed. Quantitatively, they can be interpreted as parallel thermal resistances of the trace and the rest of the board, where we treat the board approximately as a heat sink fin. These semi-analytic limits give scaling laws for the thermal resistance of the trace as function of board conductivity, heat exchange coefficient, board thickness and trace width. For the more realistic board models this simplified theory is not powerful enough as the thermal isolation between trace and first copper plane is not included.","PeriodicalId":409730,"journal":{"name":"Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130889841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Implementing compact thermal models under non-symmetric trace routing conditions 在非对称走线条件下实现紧凑的热模型

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291332

J. Galloway, S. Shidore

引用次数: 7

Simulation model development for solder joint reliability for high performance FBGA assemblies 高性能FBGA组件焊点可靠性仿真模型开发

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291338

H. Qi, Mikyoung Lee, M. Osterman, Kyujin Lee, Seyong Oh, T. Schmidt

引用次数: 7

Temperature measurements of semiconductor devices - a review 半导体器件温度测量综述

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291304

D. Blackburn

引用次数: 303

Numerical study of flow mal-distribution on the flow and heat transfer for multi-channel cold-plates 多通道冷板流动和换热过程中流动不均匀分布的数值研究

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291325

Ming-Chang Lu, Bing-Chwen Yang, Chi-Chuan Wang

引用次数: 7

Structure function evaluation of stacked dies 叠模结构功能评价

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291301

M. Rencz, V. Székely

引用次数: 72

Superlattice microrefrigerators flip-chip bonded with optoelectronic devices 超晶格微型冰箱与光电器件的倒装键合

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291323

Yan Zhang, G. Zeng, J. Piprek, A. Bar-Cohen, A. Shakouri

{"title":"Superlattice microrefrigerators flip-chip bonded with optoelectronic devices","authors":"Yan Zhang, G. Zeng, J. Piprek, A. Bar-Cohen, A. Shakouri","doi":"10.1109/STHERM.2004.1291323","DOIUrl":"https://doi.org/10.1109/STHERM.2004.1291323","url":null,"abstract":"A 3D electrothermal model was developed to study the InP-based thin film In/sub 0.53/Ga/sub 0.47/As/In/sub 0.52/Al/sub 0.48/As superlattice microrefrigerators for various device sizes, ranging from 40/spl times/40/spl mu/m/sup 2/ to 120/spl times/120/spl mu/m/sup 2/. We discussed maximum cooling and cooling power densities for current devices, analyzed the non-idealities of current devices and proposed an optimized structure. The simulation results demonstrated a maximum cooling of 30/spl deg/C with cooling power density over 300 W/cm/sup 2/ with an optimized structure based on the current device geometry. Furthermore, we also demonstrated that a maximum cooling, over 10/spl deg/C with power density over 900 W/cm/sup 2/, could be possible when the current figure of merit of InGaAs/InAlAs superlattice is enhanced five times with the non-conserved lateral momentum. Besides monolithic integration, we also propose a flip-chip bonded solution to integrate these microrefrigerator with the optoelectronic chips. Preliminary 3D electrothermal simulation will be present to analyze its cooling effects for this 2-chip integration model.","PeriodicalId":409730,"journal":{"name":"Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125424309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Thermal optimization of electronic systems using Design of Experiments based on numerical inputs 基于数值输入的电子系统热优化实验设计

Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545) Pub Date : 2004-03-09 DOI: 10.1109/STHERM.2004.1291315

T. Stewart, D. W. Stiver

{"title":"Thermal optimization of electronic systems using Design of Experiments based on numerical inputs","authors":"T. Stewart, D. W. Stiver","doi":"10.1109/STHERM.2004.1291315","DOIUrl":"https://doi.org/10.1109/STHERM.2004.1291315","url":null,"abstract":"Design optimization of realistic electronic systems is often found to be prohibitive in today's marketplace because of time constraints. Techniques, such as one-variable at a time (OFAT), that prove useful for simple designs, often fail for real-world applications. This paper describes a Design of Experiments (DoE) methodology used in conjunction with numerical inputs from a computational fluid dynamics (CFD) program to demonstrate an efficient method of optimization. As an example, the technique is used to optimize multiple aspects of the thermal performance of a next-generation network server. The outcome was that empirical prototype cycles were reduced from four to two and analytical experimentation cycles were dramatically reduced while producing a far more mature and viable cooling solution. Upon completion of the DoE, the only alterations to the design were the few minor adjustments and settings where the analytical models diverged from actual physical performance. These were rapidly finalized with the initial physical prototype, again using DoE techniques, and the final enclosure cooling architecture was completed.","PeriodicalId":409730,"journal":{"name":"Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545)","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134284583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10