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Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)最新文献

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Mixed-signal LSI relationship among measurement accuracy, yield, and test time 测量精度、良率和测试时间之间的混合信号LSI关系
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408952
H. Kohinata, M. Arai, S. Fukumoto, K. Iwasaki
{"title":"Mixed-signal LSI relationship among measurement accuracy, yield, and test time","authors":"H. Kohinata, M. Arai, S. Fukumoto, K. Iwasaki","doi":"10.1109/DBT.2004.1408952","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408952","url":null,"abstract":"As the degree of LSI integration is becoming rapidly greater and circuit size is becoming bigger, the bigger LSI test cost due to longer test time in LSI production becomes more serious. This paper discusses how much impact mixed LSI measurement accuracy improvement affects test time and LSI yield by analyzing the test results in a production test. It is a practical and effective example for the semiconductor industry to show the relationship among measurement accuracy, test time, and yield based on the actual test data.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115089504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of wafer-level spatial I/sub DDQ/ estimation methods: NNR versus NCR 晶圆级空间I/sub DDQ/估算方法的比较:NNR与NCR
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408947
S. Sabade, D. Walker
{"title":"Comparison of wafer-level spatial I/sub DDQ/ estimation methods: NNR versus NCR","authors":"S. Sabade, D. Walker","doi":"10.1109/DBT.2004.1408947","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408947","url":null,"abstract":"Extending the useful life of I/sub DDQ/ test to deep submicron technologies has been a topic of interest in recent years. I/sub DDQ/ test loses its effectiveness as the signal to noise ratio degrades due to rising background current and fault-free I/sub DDQ/ variance. Defect detection using I/sub DDQ/ test requires separation of deterministic sources of variation from defective current. Several methods that use deterministic variation in I/sub DDQ/ at the wafer level for estimating fault-free I/sub DDQ/ of a chip are proposed. This paper compares two such methods: nearest neighbor residual (NNR) and neighbor current ratio (NCR). These methods are evaluated using industrial test data for a recent technology.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132444302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Doing more with less: a recipe for rapid IDDQ development 少花钱多办事:IDDQ快速发展的秘诀
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408951
R. Ackerman
{"title":"Doing more with less: a recipe for rapid IDDQ development","authors":"R. Ackerman","doi":"10.1109/DBT.2004.1408951","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408951","url":null,"abstract":"This paper describes the method for developing and deploying IDDQ testing on two 0.18 /spl mu/m chips developed at SMA. By using the self-scaling ratio-based IDDQ technique developed by Peter Maxwell, SMA is able to effectively screen defective devices without incurring unnecessary yield penalties. This paper documents the method of generating IDDQ vectors, qualifying them through temperature analysis, characterizing the devices setting the limits, and integrating the final product into the production test. As a case study, the results of this technique are discussed as they pertain to SMA's chips.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127935643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On correlating structural tests with functional tests for speed binning 速度箱结构试验与功能试验的关联研究
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408962
Jing Zeng, M. Abadir
{"title":"On correlating structural tests with functional tests for speed binning","authors":"Jing Zeng, M. Abadir","doi":"10.1109/DBT.2004.1408962","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408962","url":null,"abstract":"The utilization of functional vectors has been an industry standard for speed binning purpose. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural test an effective alternative to functional test for speed binning, structural patterns need to correlate with functional test frequency closely. In this paper, we demonstrate the correlations between the functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/sup /spl trade// instruction set architecture.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123538536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On the potential of flush delay for characterization and test optimization 对潜在的冲洗延迟进行表征和测试优化
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408956
C. Thibeault
{"title":"On the potential of flush delay for characterization and test optimization","authors":"C. Thibeault","doi":"10.1109/DBT.2004.1408956","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408956","url":null,"abstract":"This paper explores the potential of an IC speed estimate, called flush delay, for characterization and test optimization, using Sematech Project S-121 data as a test case. This exploration leads us to conclude that: 1) characterization based on flush delay is a very efficient way to compare test methods aimed to detect IC not meeting speed specifications due to process variations; 2) (design-verification) functional testing detection capability of such slow ICs is rather poor, confirming that running at-speed random patterns is not sufficient to guarantee detection; 3) (transient fault) delay testing effectiveness exponentially decreases as IC speed increases; 4) early IC rejection and the use of two test suites with a different ordering customized for specific flush delay ranges lead to a modest (but almost free) tester time gain.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126251444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Delay testing based on transition faults propagated to all reachable outputs 基于转换错误传播到所有可达输出的延迟测试
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408958
B. Vaidya, M. Tahoori
{"title":"Delay testing based on transition faults propagated to all reachable outputs","authors":"B. Vaidya, M. Tahoori","doi":"10.1109/DBT.2004.1408958","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408958","url":null,"abstract":"Data from the test floor has shown that transition faults propagated to all reachable outputs (TARO) is more effective in detecting defective chips compared to conventional transition faults [Tseng et al. 2001]. This paper describes an efficient approach to generate tests pattern based on TARO metric using Boolean satisfiability. The problem of test pattern generation is converted to an instance of Boolean satisfiability and the recent development in the design of efficient SAT solvers has helped to speed up the process of test generation extensively. Experimental results on several benchmarks show the effectiveness of this technique.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129229599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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