On the potential of flush delay for characterization and test optimization

Abstract

This paper explores the potential of an IC speed estimate, called flush delay, for characterization and test optimization, using Sematech Project S-121 data as a test case. This exploration leads us to conclude that: 1) characterization based on flush delay is a very efficient way to compare test methods aimed to detect IC not meeting speed specifications due to process variations; 2) (design-verification) functional testing detection capability of such slow ICs is rather poor, confirming that running at-speed random patterns is not sufficient to guarantee detection; 3) (transient fault) delay testing effectiveness exponentially decreases as IC speed increases; 4) early IC rejection and the use of two test suites with a different ordering customized for specific flush delay ranges lead to a modest (but almost free) tester time gain.