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Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)最新文献

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An improved method for i/sub DDT/ testing in the presence of leakage and process variation 一种在存在泄漏和工艺变化的情况下进行i/sub DDT/测试的改进方法
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408946
A. Chehab, A. Kayssi, A. Nazer, R. Makki
{"title":"An improved method for i/sub DDT/ testing in the presence of leakage and process variation","authors":"A. Chehab, A. Kayssi, A. Nazer, R. Makki","doi":"10.1109/DBT.2004.1408946","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408946","url":null,"abstract":"We propose in this paper a testing method for CMOS circuits that is insensitive to process variations and leakage levels. This method is based on the transient supply current (i/sub DDT/) and on the observation that current levels for different circuits on a chip scale with different runs of the process. In this method, we introduce a very simple test circuit on-chip. Then, we apply a normalization procedure that allows us to use a single threshold for all chips in different processes without prior knowledge of the process to which the circuit under test belongs. Results from various circuits show that the method is capable of improving the detection capability of threshold-based i/sub DDT/ testing for faults that would otherwise go undetected due to leakage and process variation.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115023111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Calibrating power supply signal measurements for process and probe card variations 校准电源信号测量过程和探头卡的变化
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408948
D. Acharyya, J. Plusquellic
{"title":"Calibrating power supply signal measurements for process and probe card variations","authors":"D. Acharyya, J. Plusquellic","doi":"10.1109/DBT.2004.1408948","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408948","url":null,"abstract":"The power supply transient signal (I/sub DDT/) methods that we propose for defect detection and localization analyze regional signal variations introduced by defects at a set of the power supply ports on the chip under test (CUT). A significant detractor to the successful application of such methods is dealing with the signal variations introduced by process and probe card parameter variations. In this paper, we describe several calibration techniques designed to reduce the impact of these types of \"non-defect\" related chip and testing environment variations on the defect detection sensitivity of I/sub DDT/ testing methods. More specifically, calibration methods are proposed that calibrate for signal variations introduced by performance differences and by changes in the probe card RLC parameters. The calibration methodology is demonstrated through SPICE simulations and in hardware.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125235986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On the effectiveness of detecting small delay defects in the slack interval 关于在松弛区间检测小延迟缺陷的有效性
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408955
Haihua Yan, A. Singh
{"title":"On the effectiveness of detecting small delay defects in the slack interval","authors":"Haihua Yan, A. Singh","doi":"10.1109/DBT.2004.1408955","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408955","url":null,"abstract":"A new delay testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on small experimental circuits. In this paper we evaluate the effectiveness of this new approach through the simulation of injected delay faults in the ISCAS benchmark circuits. The results indicate that the new delay testing approach is orders of magnitude more effective in detecting and diagnosing smaller delay defects that increase circuit path delays by 10-50%. Thus the new methodology can address increasing concerns that failure to detect such small delay faults during test may be the cause of significant unreliability in emerging nanometer technologies.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128731843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Test volume reduction via flip-flop compatibility analysis for balanced parallel scan 通过平衡并行扫描的触发器兼容性分析减少测试体积
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408969
M. Ashouei, A. Chatterjee, A. Singh
{"title":"Test volume reduction via flip-flop compatibility analysis for balanced parallel scan","authors":"M. Ashouei, A. Chatterjee, A. Singh","doi":"10.1109/DBT.2004.1408969","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408969","url":null,"abstract":"Test generation for scan-based test of sequential circuits is typically performed by generating tests for the embedded combinational logic (ECL) and translating these into scan test vectors. However, the serial nature of scan-based test incurs significant overhead in terms of test application time. To reduce the test data volume, in this paper we propose a new algorithm for compatibility analysis of the circuit flip flops. This algorithm, when applied to parallel-scan methods such as the Illinois Scan Architecture (ILS), results in shorter and more balanced scan chains. It also eliminates the need to apply test vectors in serial mode. As a result, an average reduction of 1.4/spl times/ and a maximum reduction of 1.7/spl times/ in test data volume was obtained for the ISCAS89 benchmarks, over current versions of ILS.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128848854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fault diagnosis of a GHz CMOS LNA using high-speed ADC-based BIST 基于高速adc的BIST的GHz CMOS LNA故障诊断
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408964
J. Liobe, M. Margala
{"title":"Fault diagnosis of a GHz CMOS LNA using high-speed ADC-based BIST","authors":"J. Liobe, M. Margala","doi":"10.1109/DBT.2004.1408964","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408964","url":null,"abstract":"This paper presents a fault isolation method using the digital signatures from a LNA BIST solution. The fault localization capabilities of the functional test and data analysis methods are demonstrated by circuit level simulation. Also a discussion of the efficacy of this method is given. Results showed that only 16% of the resistive faults examined here cannot be mapped to its specification location in the LNA.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131118840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
At-speed test for path delay faults using practical techniques 用实用技术对路径延迟故障进行高速试验
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408957
Wangqi Qiu, Jing Wang, Xiang Lu, Zhuo Li, D. Walker, Weiping Shi
{"title":"At-speed test for path delay faults using practical techniques","authors":"Wangqi Qiu, Jing Wang, Xiang Lu, Zhuo Li, D. Walker, Weiping Shi","doi":"10.1109/DBT.2004.1408957","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408957","url":null,"abstract":"To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Most existing test generation tools are either inefficient in automatically identifying the longest testable paths due to the high computational complexity or do not support at-speed test using existing practical design-for-testability structures, such as scan design. In this work a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The two strategies are compared and the test generation efficiency is evaluated on the ISCAS89 benchmark circuits.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127619783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automatic test pattern generation for resistive bridging faults 电阻式桥接故障的自动测试模式生成
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/ETSYM.2004.1347652
P. Engelke, I. Polian, M. Renovell, B. Becker
{"title":"Automatic test pattern generation for resistive bridging faults","authors":"P. Engelke, I. Polian, M. Renovell, B. Becker","doi":"10.1109/ETSYM.2004.1347652","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347652","url":null,"abstract":"An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle arbitrary non-feedback bridges between two nodes, including ones detectable at higher resistance and undetectable at lower resistance, and faults requiring more than one vector for detection.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117063343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Built-in current sensor for IDDQ test 内置电流传感器IDDQ测试
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408945
Bin Xue, D. Walker
{"title":"Built-in current sensor for IDDQ test","authors":"Bin Xue, D. Walker","doi":"10.1109/DBT.2004.1408945","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408945","url":null,"abstract":"A practical built-in current sensor (BICS) design is described in this paper. This sensor system is able to monitor the IDDQ at a resolution level of 10 muA. This system can translate the current level into a digital signal, with scan chain readout. There is no system performance degradation for this sensor and its power dissipation is kept at a very low level. With the help of a self-calibration circuit, the sensor can maintain its accuracy and achieve a clock rate of over 1 GHz, for a measurement time of a few milliseconds","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"571 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116064707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
"ITRS test challenges need defect based test: fact or fiction?" “ITRS测试挑战需要基于缺陷的测试:事实还是虚构?”
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408971
J. Plusquellic
{"title":"\"ITRS test challenges need defect based test: fact or fiction?\"","authors":"J. Plusquellic","doi":"10.1109/DBT.2004.1408971","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408971","url":null,"abstract":"An important distinction between traditional \"logical fault model\" based testing and defect based testing is the potential for the latter to better handle emerging defect types and changing circuit sensitivities in VDSM circuits. ITRS gives specific examples of emerging defects including the potential for more particle-related blocked-etch resistive opens that result from the change from a subtractive aluminum process to damascene Cu. A second example derives from aggressive scaling into the nanometer domain which increases the probability of incomplete etch and the occurrence of resistive vias.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127169791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A memory built-in self-diagnosis design with syndrome compression 记忆内置自诊断设计与症候群压缩
Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004) Pub Date : 2004-04-05 DOI: 10.1109/DBT.2004.1408968
Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Yeong-Jar Chang, Wen-Ching Wu
{"title":"A memory built-in self-diagnosis design with syndrome compression","authors":"Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Yeong-Jar Chang, Wen-Ching Wu","doi":"10.1109/DBT.2004.1408968","DOIUrl":"https://doi.org/10.1109/DBT.2004.1408968","url":null,"abstract":"We present a memory built-in self-diagnosis (BISD) design that incorporates a fault syndrome compression scheme. We also have developed efficient faulty-word, faulty-row, and faulty-column identification methods, which have been incorporated in our new BISD design. Our approach reduces the amount of data that need to be transmitted from the chip under test to the automatic test equipment (ATE). It therefore reduces the ATE occupation time and the required ATE capture memory space. It also simplifies the analysis that has to be performed on the ATE. Simulation results for memories under various fault pattern distributions show that in most cases the data can be compressed to less than 6% of its original size.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131237520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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