Calibrating power supply signal measurements for process and probe card variations

Abstract

The power supply transient signal (I/sub DDT/) methods that we propose for defect detection and localization analyze regional signal variations introduced by defects at a set of the power supply ports on the chip under test (CUT). A significant detractor to the successful application of such methods is dealing with the signal variations introduced by process and probe card parameter variations. In this paper, we describe several calibration techniques designed to reduce the impact of these types of "non-defect" related chip and testing environment variations on the defect detection sensitivity of I/sub DDT/ testing methods. More specifically, calibration methods are proposed that calibrate for signal variations introduced by performance differences and by changes in the probe card RLC parameters. The calibration methodology is demonstrated through SPICE simulations and in hardware.