{"title":"\"ITRS test challenges need defect based test: fact or fiction?\"","authors":"J. Plusquellic","doi":"10.1109/DBT.2004.1408971","DOIUrl":null,"url":null,"abstract":"An important distinction between traditional \"logical fault model\" based testing and defect based testing is the potential for the latter to better handle emerging defect types and changing circuit sensitivities in VDSM circuits. ITRS gives specific examples of emerging defects including the potential for more particle-related blocked-etch resistive opens that result from the change from a subtractive aluminum process to damascene Cu. A second example derives from aggressive scaling into the nanometer domain which increases the probability of incomplete etch and the occurrence of resistive vias.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DBT.2004.1408971","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An important distinction between traditional "logical fault model" based testing and defect based testing is the potential for the latter to better handle emerging defect types and changing circuit sensitivities in VDSM circuits. ITRS gives specific examples of emerging defects including the potential for more particle-related blocked-etch resistive opens that result from the change from a subtractive aluminum process to damascene Cu. A second example derives from aggressive scaling into the nanometer domain which increases the probability of incomplete etch and the occurrence of resistive vias.