An improved method for i/sub DDT/ testing in the presence of leakage and process variation

Abstract

We propose in this paper a testing method for CMOS circuits that is insensitive to process variations and leakage levels. This method is based on the transient supply current (i/sub DDT/) and on the observation that current levels for different circuits on a chip scale with different runs of the process. In this method, we introduce a very simple test circuit on-chip. Then, we apply a normalization procedure that allows us to use a single threshold for all chips in different processes without prior knowledge of the process to which the circuit under test belongs. Results from various circuits show that the method is capable of improving the detection capability of threshold-based i/sub DDT/ testing for faults that would otherwise go undetected due to leakage and process variation.