{"title":"速度箱结构试验与功能试验的关联研究","authors":"Jing Zeng, M. Abadir","doi":"10.1109/DBT.2004.1408962","DOIUrl":null,"url":null,"abstract":"The utilization of functional vectors has been an industry standard for speed binning purpose. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural test an effective alternative to functional test for speed binning, structural patterns need to correlate with functional test frequency closely. In this paper, we demonstrate the correlations between the functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/sup /spl trade// instruction set architecture.","PeriodicalId":407554,"journal":{"name":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"On correlating structural tests with functional tests for speed binning\",\"authors\":\"Jing Zeng, M. Abadir\",\"doi\":\"10.1109/DBT.2004.1408962\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The utilization of functional vectors has been an industry standard for speed binning purpose. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural test an effective alternative to functional test for speed binning, structural patterns need to correlate with functional test frequency closely. In this paper, we demonstrate the correlations between the functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/sup /spl trade// instruction set architecture.\",\"PeriodicalId\":407554,\"journal\":{\"name\":\"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)\",\"volume\":\"69 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-04-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DBT.2004.1408962\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DBT.2004.1408962","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On correlating structural tests with functional tests for speed binning
The utilization of functional vectors has been an industry standard for speed binning purpose. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural test an effective alternative to functional test for speed binning, structural patterns need to correlate with functional test frequency closely. In this paper, we demonstrate the correlations between the functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/sup /spl trade// instruction set architecture.