对潜在的冲洗延迟进行表征和测试优化

C. Thibeault
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引用次数: 3

摘要

本文利用Sematech项目S-121数据作为测试用例,探讨了IC速度估计(称为刷新延迟)在表征和测试优化方面的潜力。这一探索使我们得出结论:1)基于刷新延迟的表征是一种非常有效的方法来比较旨在检测由于工艺变化而不满足速度规格的IC的测试方法;2)(设计验证)此类慢速ic的功能测试检测能力较差,证实高速随机模式运行不足以保证检测;(瞬态故障)延迟测试的有效性随着IC速度的增加呈指数递减;4)早期IC拒绝和使用两个不同顺序的测试套件,为特定的冲洗延迟范围定制,导致适度(但几乎免费)测试仪时间增益。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
On the potential of flush delay for characterization and test optimization
This paper explores the potential of an IC speed estimate, called flush delay, for characterization and test optimization, using Sematech Project S-121 data as a test case. This exploration leads us to conclude that: 1) characterization based on flush delay is a very efficient way to compare test methods aimed to detect IC not meeting speed specifications due to process variations; 2) (design-verification) functional testing detection capability of such slow ICs is rather poor, confirming that running at-speed random patterns is not sufficient to guarantee detection; 3) (transient fault) delay testing effectiveness exponentially decreases as IC speed increases; 4) early IC rejection and the use of two test suites with a different ordering customized for specific flush delay ranges lead to a modest (but almost free) tester time gain.
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