Proceedings. SOS/SOI Technology Workshop最新文献_第2页

Monitoring of heavy metals in as-implanted SIMOX with surface photovoltage 表面光电压法监测砷注入SIMOX中重金属含量

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95402

L. Jastrzebski, R. Soydan

引用次数: 7

Low defect, high quality SIMOX material for bipolar device applications 用于双极器件的低缺陷、高质量SIMOX材料

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95395

F. Namavar, E. Cortesi, P. Sioshansi

{"title":"Low defect, high quality SIMOX material for bipolar device applications","authors":"F. Namavar, E. Cortesi, P. Sioshansi","doi":"10.1109/SOI.1988.95395","DOIUrl":"https://doi.org/10.1109/SOI.1988.95395","url":null,"abstract":"The threading dislocation densities of 10/sup 8//cm/sup 2/ to 10/sup 10//cm/sup 2/ that are typical of SIMOX material are detrimental for bipolar structures and orders-of-magnitude reduction of defect density is still required to permit SIMOX (separation by implanted oxygen) material to be acceptable for high-performance bipolar and analog devices. Two methods have been developed to produce low-defect SIMOX wafers. In the first method, threading dislocation defects are reduced by low-dose Ge implantation and subsequent solid-phase epitaxial (SPE) regrowth. Ge implantation produces a strained and amorphized layer that during the subsequent SPE acts as an artificial interface and deflects or stops the propagation of threading dislocations. In the second method, threading dislocations are prevented by a multiple low-dose implantation and high-temperature annealing process. No defects were observed for implantation with doses up to 8*10/sup 17/ O/sup +//cm/sup 2/, and threading dislocation density has been reduced by three to four orders of magnitude. Continuous and uniform buried layers are formed with about 65% of the dose required by the standard SIMOX process. Preliminary results have shown that by use of these methods low defect, superior quality, SIMOX wafers for submicron CMOS and bipolar device applications can be produced.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116064077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Numerical analysis of island-edge effects in SOS MOSFETs SOS mosfet中岛边效应的数值分析

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95405

Q. Lu, Changtong Huang

引用次数: 0

A VHSIC compatible CMOS/SOS cell family 一个VHSIC兼容CMOS/SOS电池系列

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95441

M. J. Fresnadillo Martínez, R. W. Polkinghorn

引用次数: 0

Enhanced elimination of extended defects associated with P/sup +/ and Ga/sup +/ implantation of SIMOX 增强消除与P/sup +/和Ga/sup +/ SIMOX植入相关的扩展缺陷

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95422

K. Jones, D. Venables, C. R. Horne, G. Davis

{"title":"Enhanced elimination of extended defects associated with P/sup +/ and Ga/sup +/ implantation of SIMOX","authors":"K. Jones, D. Venables, C. R. Horne, G. Davis","doi":"10.1109/SOI.1988.95422","DOIUrl":"https://doi.org/10.1109/SOI.1988.95422","url":null,"abstract":"Summary form only given. Ion implantation doping of annealed SIMOX (separation by implantation of oxygen) wafers has been investigated. The dose of the phosphorus and gallium implants, 1*10/sup 16//cm/sup 2/ and 5*10/sup 14//cm/sup 2/, respectively, was such that the peak concentration exceeded the impurity solid solubility at the subsequent annealing temperature of 900 degrees C. The energy was adjusted so that the top 700 AA of the 1300 AA superficial silicon layer was amorphized. Both plan-view and cross-sectional TEM were used to investigate the subsequent defect annealing kinetics. No category III (regrowth related) defects were observed upon low-temperature (550 degrees C) solid phase epitaxy. Diffuse dark field TEM results indicate that a fine dispersion of oxide particles exists in the superficial silicon layer. Upon 900 degrees C annealing, enhanced elimination of the category II (end of range) dislocation loops was observed in both the SIMOX and silicon control wafers. This indicates that the high oxygen concentration in the superficial silicon layer does not retard the enhanced defect dissolution process. However, Hall effect and sheet resistivity results indicate that there is a significant decrease in the free carrier mobility as well as the electrical activation of these dopants in SIMOX.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134562323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A performance comparison of advanced SOI technologies 先进SOI技术的性能比较

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95448

D. Adams, M. Austin, R. Rai-Choudhury, J. Hwang

{"title":"A performance comparison of advanced SOI technologies","authors":"D. Adams, M. Austin, R. Rai-Choudhury, J. Hwang","doi":"10.1109/SOI.1988.95448","DOIUrl":"https://doi.org/10.1109/SOI.1988.95448","url":null,"abstract":"Summary form only given. Devices have been fabricated using conventional SOS, rapid thermal anneal (RTA) SOS, solid-phase epitaxy and regrowth (SPEAR) SOS, RTA-SPEAR SOS, separation by implantation of oxygen (SIMOX), RTA-SIMOX, and zone-melt recrystallization (ZMR) wafers. The process sequence used was a double-level-metal 1.25- mu m CMOS/SOS process. A comprehensive test vehicle featuring 16 K and 64 K SRAMs was used to allow both parametric and functional characterization. For 0.3- mu m silicon film thickness on SOS, SPEAR processing resulted in a 30% improvement in carrier mobilities and a 10-20% improvement in device saturation currents over conventional SOS. No significant leakage improvement was observed. RTA processing at 1390 degrees C has shown potential for performance enhancement on SOS. Mobility improvements of 10-20% have been demonstrated, while drain leakage was unchanged. Preliminary SIMOX results have indicated improvements of 50% for electron mobilities, with hole mobilities unchanged over conventional SOS. Drain leakage was two orders of magnitude lower. Characterization results have also been obtained for ZMR, RTA-SPEAR SOS, improved SPEAR-SOS, and improved SIMOX wafers.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126031531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Radiation hardened VHSIC CMOS/SOS process 抗辐射VHSIC CMOS/SOS工艺

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95451

L. Chung, L. Tocci, P. Liu, J. Fraser, J. White, R. Colesworthy, J. Brandewie, R. Kjar

{"title":"Radiation hardened VHSIC CMOS/SOS process","authors":"L. Chung, L. Tocci, P. Liu, J. Fraser, J. White, R. Colesworthy, J. Brandewie, R. Kjar","doi":"10.1109/SOI.1988.95451","DOIUrl":"https://doi.org/10.1109/SOI.1988.95451","url":null,"abstract":"Summary form only given, as follows. A vertical wall mesa process has been used to fabricate radiation-hard CMOS/SOS circuits for military applications. However, scaling of this process to smaller geometry has to include not only lateral dimensions but also vertical dimensions. For 1.6- mu m design rules, a radiation-hard process has been developed with 1.25- mu m effective channel lengths and 250-AA gate oxide. Two asynchronous 16 K SRAMs with 2.0- mu m and 1.6- mu m design rules, respectively, were used as test vehicles along with an extensive design rules verification module and a radiation test module. A defect monitor structure was also incorporated for process monitoring, failure analysis, and yield prediction. Gate oxide reliability was greatly improved by treating the edges of vertical islands using a modified isolation oxidation technique. Threshold voltage shifts as low as -0.3 V and -0.5 V at 1 Mrad (SiO/sub 2/) total dose for nFETs and pFETs, respectively, were achieved. A low radiation-induced edge leakage of 15 nA/edge, primarily due to thin gate oxide, was also achieved. 16 K SRAM functionality beyond 1 Mrad total dose was demonstrated.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133880919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Performance of SIMOX transistors at very low temperatures SIMOX晶体管在极低温下的性能

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95446

T. Elewa, F. Balestra, S. Cristoloveanu, A. Auberton-Herve, J. Davis

引用次数: 3

Comparison of fabrication methods for bonded wafer SOI 键合硅片SOI制备方法的比较

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95430

J. Delgado, G. Rouse, C. McLachlan, S. Gaul

{"title":"Comparison of fabrication methods for bonded wafer SOI","authors":"J. Delgado, G. Rouse, C. McLachlan, S. Gaul","doi":"10.1109/SOI.1988.95430","DOIUrl":"https://doi.org/10.1109/SOI.1988.95430","url":null,"abstract":"Summary form only given. The reduction of collector series resistance in bipolar devices and the prevention of back-gate effects in MOS devices is commonly realized through the use of highly doped buried layers and retrograde implanted wells, respectively. For device applications requiring a thick SOI layer (approximately 10 mu m), this can be achieved by using back-side processing in a wafer-bounding technique. While bipolar devices have been successfully fabricated using this method, the resulting back-side nonuniformities can reduce bounding yield. This shows up as microdebonding after the trench etch used for lateral isolation. Other drawbacks to back-side bonding are difficult front-to-back alignment and a relatively large variation in layer thickness (+1.5 mu m across a 4-in. slice) due to the grind/polish step used for planarization. An improved method of manufacturing thick bonded SOI material using an epitaxial layer on a thin bonded substrate eliminates many of the drawbacks to the back-side bonding approach. This epi-on-bonded method results in an all-frontside material process suitable for use in a complementary bipolar or BICMOS technology.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"9 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132846760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Selected area channeling pattern, defect etch and lifetime study of silicon implanted with oxygen 氧注入硅的选区通道模式、缺陷蚀刻及寿命研究

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95434

P. Roitman, G. Davis, P. Nelson, O. Stafsudd

引用次数: 0