Proceedings. SOS/SOI Technology Workshop最新文献_第3页

Measurement and modelling of arsenic and boron diffusion in oxygen implanted silicon-on-insulator (SOI) layers 砷和硼在氧注入绝缘体上硅(SOI)层中扩散的测量和模拟

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95416

D. J. Godfrey, R. Chater, A. K. Robinson, P.D. Augustus, J. R. Alderman, J.R. Davis, J. Kilner, P. Hemment

引用次数: 0

Silicon-on-insulator by wafer bonding and etch-back 通过晶圆键合和蚀刻回制的绝缘体上硅

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95391

W. Maszara, G. Goetz, A. Caviglia, J.B. McKitterick

{"title":"Silicon-on-insulator by wafer bonding and etch-back","authors":"W. Maszara, G. Goetz, A. Caviglia, J.B. McKitterick","doi":"10.1109/SOI.1988.95391","DOIUrl":"https://doi.org/10.1109/SOI.1988.95391","url":null,"abstract":"A novel silicon-on-insulator technique utilizing the bonding of oxidized silicon wafers has been investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces, which had been contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60-85 erg/cm/sup 2/ at room temperature to approximately=2200 erg/cm/sup 2/ at 1400 degrees C, which is in the same range as the cohesive energy of bulk quartz. The strength was essentially independent of the bond time. Bonds created during a 10 s annealing at 800 degrees C were strong enough to withstand both the thinning of the top wafer to the desired thickness and the subsequent device processing. Three distinct phases of the bonding process were observed. The electrical properties of the bond between the wafers were tested using MOS capacitors. The results were consistent with a negative charge density at the bond interface of approximately 10/sup 11/ cm/sup -2/. A double etch-back procedure was used to thin the device wafer to the desired thickness. The characteristics of the resulting film are described. CMOS devices made in a 0.3- mu m-thick layer had subthreshold slopes of 68 mV/decade (for both n- and p-channel MOS transistors). The effective carrier lifetime was >30 mu s in 300-nm-thick Si films, and the interface state density at the Si-film/buried oxide interface was <5*10/sup 10/ cm/sup -2/.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123859007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

The design and fabrication of a 3D smart motor controller in ZMR material 基于ZMR材料的三维智能电机控制器的设计与制造

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95437

A. Mathewson

引用次数: 1

SIMOX and VLSI high speed and rad hard applications: discussion of floating body effects and circuits optimization SIMOX和VLSI高速和硬应用:浮体效应和电路优化的讨论

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95427

A. Auberton-Herve

引用次数: 6

A comparison of fully depleted SOI-CMOS transistors in FIPOS and SIMOX substrates FIPOS和SIMOX衬底上全耗尽SOI-CMOS晶体管的比较

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95413

N. Thomas, J.R. Davis, K. Reeson, P. Hemment, J. Keen, J. G. Castledine, D. Brumhead, M. Goulding, J. Alderman, J. Farr, L.G. Earwalker

{"title":"A comparison of fully depleted SOI-CMOS transistors in FIPOS and SIMOX substrates","authors":"N. Thomas, J.R. Davis, K. Reeson, P. Hemment, J. Keen, J. G. Castledine, D. Brumhead, M. Goulding, J. Alderman, J. Farr, L.G. Earwalker","doi":"10.1109/SOI.1988.95413","DOIUrl":"https://doi.org/10.1109/SOI.1988.95413","url":null,"abstract":"Summary form only given. To maximize the performance of SOI-CMOS transistors, the silicon film under the gate should be depleted, which requires the use of thin-film SOI material. The authors have produced 1- mu m thin-film SOI-CMOS transistors in wafers produced by separation by oxygen implantation (SIMOX) and by oxidation of porous silicon (FIPOS) processes. The silicon film thicknesses were approximately 140 nm for the SIMOX wafers and 100 nm for the FIPOS wafers. The basic characteristics of transistors in the two types of material are similar, with high gains and current drives, near-ideal subthreshold slopes, and low junction leakages. In both cases the characteristics are free from the kink seen in partially depleted devices. Both types of n-channel device exhibit slight negative output resistance at high gate voltages. Low-field-inversion mobilities are comparable for the two types of SOI. For SIMOX material the n- and p-channel mobilities are 580 and 220 cm/sup 2//V/s, respectively; for FIPOS the figures are 520 and 235 cm/sup 2//V/s. The back channel mobilities of SIMOX transistors are over 90% of the front channel values; for FIPOS the back channel mobilities are 55-60% of the values for the front channels. The values of Delta L for both front and back channels and for both types of material that show no anomalous lateral diffusion of source/drain dopants has occurred.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122850094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Ultra-thin high quality SOS films 超薄高品质SOS薄膜

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95389

D. Dumin, S. Dabral, M. Freytag, P. Robertson, G. Carver, D. Novotny

{"title":"Ultra-thin high quality SOS films","authors":"D. Dumin, S. Dabral, M. Freytag, P. Robertson, G. Carver, D. Novotny","doi":"10.1109/SOI.1988.95389","DOIUrl":"https://doi.org/10.1109/SOI.1988.95389","url":null,"abstract":"SOS films 0.2- mu m, 0.5- mu m, and 1.0- mu m thick have been grown at rates from 0.5 to 26 mu m/min in a single-wafer epitaxial reactor. Both p-channel and n-channel MOS transistors were fabricated, using n/sup +/ poly-Si as a gate material. The channel lengths and widths were 20 mu m and 250 mu m, respectively. The p-channel transistors were enhancement devices with threshold voltages around -1.2 V. The n-channel transistors were depletion devices with threshold voltages around 0 V. The 1.0- mu m-thick films produced transistors with values of mu /sub n/ around 700 cm/sup 2//V-s and mu /sub p/ around 275 cm/sup 2//V-s and almost independent of growth rate. The 0.5- mu m-thick films produced transistors with lower mobilities until the growth rate exceeded 8 mu m/min. Films grown at growth rates above 8 mu m/min produced n-channel and p-channel transistors with mobilities of 700 cm/sup 2//V-s and 250 cm/sup 2//V-s, respectively. The 0.2- mu m-thick films produced lower mobility transistors until the growth rates exceeded 8 mu m/min, at which time the mobilities also reached the above-quoted values. Several films 0.1- mu m-thick grown at growth rates above 10 mu m/min had equally high mobilities. The subthreshold characteristics of these transistors indicated surface-state densities of about 10/sup 11/ states/cm/sup 2/. Leakage currents were less than 10/sup -11/ A. The mobility dropped about 20% from the threshold voltage to gate voltages of 5 V. The mobilities in the saturation region were about 20% less than the mobilities in the linear region.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"84 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113971963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Total dielectric isolation (TDI) of silicon device islands by a single O/sup +/ implantation stage 单O/sup +/注入阶段硅器件岛的总介电隔离(TDI)

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95432

A. K. Robinson, K. Reeson, P. Hemment, N. Thomas, J.R. Davis, K. Christensen, C. Marsh, G. Booker, J. Kilner, R. Chater

引用次数: 0

Film uniformly in bond and etch-back silicon on insulator (BESOI) 粘接均匀成膜，绝缘体上可蚀刻回硅(BESOI)

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95429

C. Hunt

引用次数: 0

Silicon electrochemistry related to the formation of porous silicon 与硅电化学有关的多孔硅的形成

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95393

M. Kelly, T. Guilinger, S. S. Tsao

引用次数: 1

Self aligned doping of mesa sidewalls for SOI transistors SOI晶体管台面侧壁的自对准掺杂

Proceedings. SOS/SOI Technology Workshop Pub Date : 1988-10-03 DOI: 10.1109/SOI.1988.95404

M. Matloubian, B. Mao, G. Pollack

引用次数: 3