{"title":"基于ZMR材料的三维智能电机控制器的设计与制造","authors":"A. Mathewson","doi":"10.1109/SOI.1988.95437","DOIUrl":null,"url":null,"abstract":"It has been found, from the results of a design study carried out out on three-dimensional (3-D) SOI integration, that the expected improvements in speed and packing density over bulk technology are not large enough to make two-level 3-D viable in the context of VLSI circuits. However, the 3-D technique has been identified as having a major role in the area of mixed technology applications. The design and fabrication of a smart power-test-bed demonstration circuit, to evaluate the feasibility of this approach, are described. For this circuit a 50-70-V bulk DMOS power technology and a 3- mu m SOI CMOS controlling logic have been developed. To provide maximum design flexibility both of these technologies have been combined in a 3-D SOI gate array, suitable for semicustom interfacing and medium current/voltage driving applications. The evaluation circuit is configured as a 50-V/1-A stepper motor controller.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"389 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"The design and fabrication of a 3D smart motor controller in ZMR material\",\"authors\":\"A. Mathewson\",\"doi\":\"10.1109/SOI.1988.95437\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It has been found, from the results of a design study carried out out on three-dimensional (3-D) SOI integration, that the expected improvements in speed and packing density over bulk technology are not large enough to make two-level 3-D viable in the context of VLSI circuits. However, the 3-D technique has been identified as having a major role in the area of mixed technology applications. The design and fabrication of a smart power-test-bed demonstration circuit, to evaluate the feasibility of this approach, are described. For this circuit a 50-70-V bulk DMOS power technology and a 3- mu m SOI CMOS controlling logic have been developed. To provide maximum design flexibility both of these technologies have been combined in a 3-D SOI gate array, suitable for semicustom interfacing and medium current/voltage driving applications. The evaluation circuit is configured as a 50-V/1-A stepper motor controller.<<ETX>>\",\"PeriodicalId\":391934,\"journal\":{\"name\":\"Proceedings. SOS/SOI Technology Workshop\",\"volume\":\"389 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-10-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. SOS/SOI Technology Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.1988.95437\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. SOS/SOI Technology Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1988.95437","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design and fabrication of a 3D smart motor controller in ZMR material
It has been found, from the results of a design study carried out out on three-dimensional (3-D) SOI integration, that the expected improvements in speed and packing density over bulk technology are not large enough to make two-level 3-D viable in the context of VLSI circuits. However, the 3-D technique has been identified as having a major role in the area of mixed technology applications. The design and fabrication of a smart power-test-bed demonstration circuit, to evaluate the feasibility of this approach, are described. For this circuit a 50-70-V bulk DMOS power technology and a 3- mu m SOI CMOS controlling logic have been developed. To provide maximum design flexibility both of these technologies have been combined in a 3-D SOI gate array, suitable for semicustom interfacing and medium current/voltage driving applications. The evaluation circuit is configured as a 50-V/1-A stepper motor controller.<>