{"title":"A rapid assessment technique for SOI substrates","authors":"S. Hall, L. Mcdaid, W. Eccleston, J. Alderman","doi":"10.1109/SOI.1988.95403","DOIUrl":"https://doi.org/10.1109/SOI.1988.95403","url":null,"abstract":"Anomalous device behaviour such as the kink effect is related to device parameters such as carrier lifetime and device dimensions. Simple experimental techniques to extract these parameters have been developed. The basic test structure consists of an MOS capacitor fabricated by evaporating an array of metal dots onto an oxidized SOI substrate. The first measurement consists of a single, high-frequency capacitance-voltage plot, from which the thicknesses of buried oxide and active body region and substrate doping can be deduced. Capacitance transient measurements are then performed in which the relaxation of the SOI capacitor system after a fast-rise time, depleting-voltage step is monitored. The transient is affected by charge generation processes occurring in both the substrate and the body. A physical model has been developed to account for these phenomena, and the validity of the techniques has been demonstrated by independent measurements.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128001228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SIMOX characterization by photoinduced transient spectroscopy","authors":"S. Mayo, J. Lowney, P. Roitman","doi":"10.1109/SOI.1988.95418","DOIUrl":"https://doi.org/10.1109/SOI.1988.95418","url":null,"abstract":"The technique of photoinduced transient spectroscopy (PITS) has been applied to the study of deep-level traps in SIMOX (separation by implantation of oxygen) silicon","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125126765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Studies of defects and buried oxides in SIMOX based SOI materials","authors":"F. Brady, H. Chen, S.S. Li, W. Krull","doi":"10.1109/SOI.1988.95435","DOIUrl":"https://doi.org/10.1109/SOI.1988.95435","url":null,"abstract":"A detailed study of detects and buried-oxide interface properties has been made on SOI devices fabricated from SIMOX (separation of implantation of oxygen) wafers implanted by Eaton NV-200 in 1986 and devices built from more recently acquired wafers. The analysis includes C-V and C-t measurements on buried-oxide capacitors, and I-V, C-V, and DLTS measurements on n/sup +//p and p/sup +//n diodes fabricated on SIMOX substrates. The old SIMOX wafers received oxygen implants of 1.8 or 2.0*10/sup 18/ cm/sup -2/ and were annealed at 1250 degrees C for 2 h. The oxygen dose for the recent SIMOX wafers was also 1.8*10/sup 18/, but it received a 1285 degrees C, 2-h anneal. Improved characteristics are reported for new SIMOX devices and are attributed in part to the higher postimplant annealing temperature used. Another possible reason for the increase in device quality is a reduction in the amount of metallic impurity contamination during oxygen implantation. Therefore, the improved performance and characteristics of the new devices most likely reflect lower densities of oxygen-related defects and metallic impurities.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132240638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low frequency noise in SIMOX MOSFETs","authors":"R. Fox, S. Lee","doi":"10.1109/SOI.1988.95410","DOIUrl":"https://doi.org/10.1109/SOI.1988.95410","url":null,"abstract":"An extensive study has been made of low-frequency noise in MOSFETs built in a variety of SIMOX (separation by implanted oxygen) processes. Most of the devices studied showed very high noise levels dominated by generation-recombination noise. Among the devices measured were NMOS and PMOS FETs with superficial Si layers ranging in thickness from 0.3 mu m (no epi layer) to 2.5 mu m (with epi). SIMOX implant doses ranged from 1.4*10/sup 18/ cm/sup -2/ to 1.8*10/sup 18/ cm/sup -2/. Anneal times varied from 3 to 16 hours, and anneal temperatures varied from 1150 degrees C to 1275 degrees C. The shape and level of the measured noise spectra varied strongly as a function of back or front surface potential. Classic 1/f noise was not observed and was probably masked by other processes. Over the measured frequency range (10 Hz to 10 kHz) the noise was dominated by fluctuations in the channel carrier concentration due to trapping. From the shape of the noise spectra and their strong dependence on surface potential, it is concluded that the traps are not located in either the top or bottom oxide layers but in the bulk. A few distinct trap levels, each with an associated time constant, interact most strongly with channel carriers when the Fermi level aligns with the trap level, which accounts for the strong dependence on surface potential. It appears likely that these traps are associated with the dislocations typically generated in the SIMOX process.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114976171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Two-dimensional numerical device simulation for SOI MOSFETs","authors":"Y. Iriye, T. Ishizuka","doi":"10.1109/SOI.1988.95417","DOIUrl":"https://doi.org/10.1109/SOI.1988.95417","url":null,"abstract":"The use of a two-dimensional device simulator has been analyzed for SOI MOSFETs. The drain current kink effect and a phenomenon for substrate floating devices have been simulated. The governing equations have been solved numerically by a finite-difference method.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126489142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of process variants on SEU tolerance of CMOS/SOS circuits","authors":"G. Brucker, K. Strater, H. Veloric","doi":"10.1109/SOI.1988.95443","DOIUrl":"https://doi.org/10.1109/SOI.1988.95443","url":null,"abstract":"Summary form only given. The impact of several process variants on single-event-upset (SEU) tolerance of the RCA/GE 6167/RZ, 16 K CMOS/SOS SRAM was determined. The RAMs were fabricated with a 3- mu m gate process. In epitaxial films consisting of three crystal structures and two p impurity profiles. The devices were evaluated in the SEU test facility at Brookhaven Laboratory. Although some test cells showed improvements in total dose hardness, there was no degradation in SEU tolerance. The SEU tolerance of a CMOS and CMOS/SOS error detection and correction circuit was also evaluated. The circuits were gate arrays processed with a 1.2- mu m gate process. The circuit could not be upset up to a cross section of 149 MeV-cm/sup 2//mg. The CMOS circuit has an error rate approximately 4E-7/day. The SEU test data are summarized in a table.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117335219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Asymmetry in the charge injection of SIMOX interfaces","authors":"C. Patel, J. Butcher","doi":"10.1109/SOI.1988.95433","DOIUrl":"https://doi.org/10.1109/SOI.1988.95433","url":null,"abstract":"Summary form only given. The charge transport in the synthesized buried oxide of a SIMOX (separation by implantation of oxygen) structure shows deviation from the ideal Fowler-Nordheim dependence. An observed asymmetry of the injecting layers associated with the top and bottom Si/SiO/sub 2/ interfaces is reported. This observation is compatible with optical measurements which reveal the presence of an intermediate layer (10-40-nm thick) at the interface between the buried oxide and the bulk silicon substrate. Sequential ramp I-V measurements show a large reservoir of positive charge trapping centers. Little is known about the spatial distribution of the centers and their dependence on the high-energy oxygen implantation parameters. The sequential ramping measurements demonstrate maximum charge storage capacity of the buried oxide. The electron injection from the cathode is enhanced at a relatively low average field, and the current levels are higher by several orders than those of thermal SiO/sub 2/. This observation is compatible with silicon-rich-SiO/sub 2/ injectors. The effective barrier heights are considerably lower than the thermal SiO/sub 2/ barrier height. Also observed is a difference in the effective barrier heights at the top and bottom Si/SiO/sub 2/ interfaces, which leads to asymmetry in charge injection.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133511803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved SOS by rapid thermal annealing and solid phase epitaxial regrowth","authors":"P. Rai-Choudhury, P. Vasudev, J. Phillips","doi":"10.1109/SOI.1988.95428","DOIUrl":"https://doi.org/10.1109/SOI.1988.95428","url":null,"abstract":"Summary form only given. CMOS circuits made from conventional SOS material frequently suffer from high bulk and back channel leakage. An attempt has been made to improve the quality of the bulk material by a combination of rapid thermal annealing (RTA) and solid-phase epitaxial regrowth (SPEAR). The baseline, the RTA, and the RTA/SPEAR SOS layers were examined for Al redistribution by secondary ion mass spectrometry and spreading resistance measurements. The quality of the material was examined by Rutherford backscattering and transmission electron microscopy. Electrical evaluation was done by wafer mapping using four point probe sheet resistance and contactless sheet conductance using Lehighton probes. Channel mobilities were measured using MOSFETs fabricated on these materials. High-temperature RTA increases the Al content of the material, which can be removed by subsequent processing. In most samples, however, Al distribution was found to be patchy. The Al content of the processed RTA/SPEAR samples was much lower than that in any conventionally processed SOS material.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130129433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Dunne, S. O'Flanagan, J. Donnelly, C. Cahill, A. Mathewson, P. Timans, R. Mcmahon, H. Ahmed
{"title":"Fully stacked 3D devices in electron beam recrystallised material","authors":"B. Dunne, S. O'Flanagan, J. Donnelly, C. Cahill, A. Mathewson, P. Timans, R. Mcmahon, H. Ahmed","doi":"10.1109/SOI.1988.95440","DOIUrl":"https://doi.org/10.1109/SOI.1988.95440","url":null,"abstract":"Summary form only given. The use of a dual-electron-beam recrystallization system to form the SOI material for the fabrication of fully stacked devices is described. One electron beam is rapidly raster scanned across the underside of the wafer to provide uniform, isothermal heating to a background temperature of 950 degrees C. The second electron beam is incident from above and is formed into a line by scanning with a 100-kHz triangle-wave deflection signal. One row of die is recrystallized with each sweep of the beam, and the wafer is mechanically stepped sideways between sweeps to recrystallize complete wafers, with the background heating following to maintain thermal uniformity. The best quality material results when the regrowth from the melt is seeded from the underlying substrate through windows cut in the isolating oxide. The structure of the fully stacked devices fabricated (SMOS) is illustrated. This structure contains p-channel MOS transistors in the bulk silicon and n-channel devices in the SOI layer directly above. An example of a transfer characteristic from a stacked inverter is given, showing that the recrystallization step does not significantly affect the bulk device performance.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134124658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Deep traps in very thin SIMOX MOSFET by current DLTS","authors":"D. Ioannou, P. Mclarty, H. Hughes, J. Colinge","doi":"10.1109/SOI.1988.95400","DOIUrl":"https://doi.org/10.1109/SOI.1988.95400","url":null,"abstract":"Summary form only given. The study of deep levels in thin SIMOX (separation by implanted oxygen) films present difficulties due to the series resistance present when standard capacitance deep-level transient spectroscopy (DLTS) is used. The authors have developed a theory of current DLTS appropriate for the study of enhancement MOSFETs, for the case of both fully depleted and not fully depleted transistors. They have found that careful biasing of the device during measurement and a prudent choice of rate windows can effectively suppress the current overshoot, which if present leads to erroneous DLTS spectra. They have also found that in fully depleted structures, bulk and back interface traps are easily distinguished by applying various substrate biases. The authors have applied this technique to study the effect of various postimplantation annealing treatments on the deep levels in both n-channel and p-channel transistors and have observed a number of traps, including the Pb center and one due to iron (0.45 eV above the valence band edge).<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131460078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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