Comparison of fabrication methods for bonded wafer SOI

Abstract

Summary form only given. The reduction of collector series resistance in bipolar devices and the prevention of back-gate effects in MOS devices is commonly realized through the use of highly doped buried layers and retrograde implanted wells, respectively. For device applications requiring a thick SOI layer (approximately 10 mu m), this can be achieved by using back-side processing in a wafer-bounding technique. While bipolar devices have been successfully fabricated using this method, the resulting back-side nonuniformities can reduce bounding yield. This shows up as microdebonding after the trench etch used for lateral isolation. Other drawbacks to back-side bonding are difficult front-to-back alignment and a relatively large variation in layer thickness (+1.5 mu m across a 4-in. slice) due to the grind/polish step used for planarization. An improved method of manufacturing thick bonded SOI material using an epitaxial layer on a thin bonded substrate eliminates many of the drawbacks to the back-side bonding approach. This epi-on-bonded method results in an all-frontside material process suitable for use in a complementary bipolar or BICMOS technology.<>