{"title":"A performance comparison of advanced SOI technologies","authors":"D. Adams, M. Austin, R. Rai-Choudhury, J. Hwang","doi":"10.1109/SOI.1988.95448","DOIUrl":null,"url":null,"abstract":"Summary form only given. Devices have been fabricated using conventional SOS, rapid thermal anneal (RTA) SOS, solid-phase epitaxy and regrowth (SPEAR) SOS, RTA-SPEAR SOS, separation by implantation of oxygen (SIMOX), RTA-SIMOX, and zone-melt recrystallization (ZMR) wafers. The process sequence used was a double-level-metal 1.25- mu m CMOS/SOS process. A comprehensive test vehicle featuring 16 K and 64 K SRAMs was used to allow both parametric and functional characterization. For 0.3- mu m silicon film thickness on SOS, SPEAR processing resulted in a 30% improvement in carrier mobilities and a 10-20% improvement in device saturation currents over conventional SOS. No significant leakage improvement was observed. RTA processing at 1390 degrees C has shown potential for performance enhancement on SOS. Mobility improvements of 10-20% have been demonstrated, while drain leakage was unchanged. Preliminary SIMOX results have indicated improvements of 50% for electron mobilities, with hole mobilities unchanged over conventional SOS. Drain leakage was two orders of magnitude lower. Characterization results have also been obtained for ZMR, RTA-SPEAR SOS, improved SPEAR-SOS, and improved SIMOX wafers.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. SOS/SOI Technology Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1988.95448","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Summary form only given. Devices have been fabricated using conventional SOS, rapid thermal anneal (RTA) SOS, solid-phase epitaxy and regrowth (SPEAR) SOS, RTA-SPEAR SOS, separation by implantation of oxygen (SIMOX), RTA-SIMOX, and zone-melt recrystallization (ZMR) wafers. The process sequence used was a double-level-metal 1.25- mu m CMOS/SOS process. A comprehensive test vehicle featuring 16 K and 64 K SRAMs was used to allow both parametric and functional characterization. For 0.3- mu m silicon film thickness on SOS, SPEAR processing resulted in a 30% improvement in carrier mobilities and a 10-20% improvement in device saturation currents over conventional SOS. No significant leakage improvement was observed. RTA processing at 1390 degrees C has shown potential for performance enhancement on SOS. Mobility improvements of 10-20% have been demonstrated, while drain leakage was unchanged. Preliminary SIMOX results have indicated improvements of 50% for electron mobilities, with hole mobilities unchanged over conventional SOS. Drain leakage was two orders of magnitude lower. Characterization results have also been obtained for ZMR, RTA-SPEAR SOS, improved SPEAR-SOS, and improved SIMOX wafers.<>