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Proceedings of Technical Program of 2012 VLSI Technology, System and Application最新文献

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Stabilization of resistive switching with controllable self-compliant Ta2O5-based RRAM 基于ta2o5的可控自适应RRAM的阻性开关稳定
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-TSA.2012.6210099
W. Chen, T. Y. Wu, S. Y. Yang, W. H. Liu, H. Y. Lee, Y. S. Chen, C. Tsai, P. Gu, K. Tsai, H. Wei, P. S. Chen, Y. H. Wang, F. Chen, M. Tsai
{"title":"Stabilization of resistive switching with controllable self-compliant Ta2O5-based RRAM","authors":"W. Chen, T. Y. Wu, S. Y. Yang, W. H. Liu, H. Y. Lee, Y. S. Chen, C. Tsai, P. Gu, K. Tsai, H. Wei, P. S. Chen, Y. H. Wang, F. Chen, M. Tsai","doi":"10.1109/VLSI-TSA.2012.6210099","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210099","url":null,"abstract":"Ta/Ta<sub>2</sub>O<sub>5</sub> RRAMs show self-compliant characteristics in some Ta or Ta<sub>2</sub>O<sub>5</sub> thickness range but Ti/TaO<sub>x</sub> RRAMs always need current compliance due to totally consumption of SC conduction layer.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127298747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology PMOSFET布局依赖于嵌入式SiGe源/漏极在POLY和STI边缘在32/28nm CMOS技术
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-TSA.2012.6210152
L. Song, Y. Liang, H. Onoda, C. W. Lai, T. Wallner, A. Pofelski, C. Gruensfelder, E. Josse, T. Okawa, J. Brown, R. Williams, J. Holt, J. W. Weijtmans, B. Greene, H. Utomo, S. Lee, D. Nair, Q. Zhang, C. Zhu, X. Wu, M. Sherony, Y. Lee, W. Henson, R. Divakaruni, E. Kaste
{"title":"PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology","authors":"L. Song, Y. Liang, H. Onoda, C. W. Lai, T. Wallner, A. Pofelski, C. Gruensfelder, E. Josse, T. Okawa, J. Brown, R. Williams, J. Holt, J. W. Weijtmans, B. Greene, H. Utomo, S. Lee, D. Nair, Q. Zhang, C. Zhu, X. Wu, M. Sherony, Y. Lee, W. Henson, R. Divakaruni, E. Kaste","doi":"10.1109/VLSI-TSA.2012.6210152","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210152","url":null,"abstract":"The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126183530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Transforming memory systems: Optimizing for client value on emerging workloads 转换内存系统:在新兴工作负载上优化客户端价值
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-DAT.2012.6212609
K. Nowka
{"title":"Transforming memory systems: Optimizing for client value on emerging workloads","authors":"K. Nowka","doi":"10.1109/VLSI-DAT.2012.6212609","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2012.6212609","url":null,"abstract":"Computing systems are increasingly being transformed to better satisfy the demands of cloud computing, Big Data, and deep, sophisticated analytics applications. These applications are driving an explosion in volume of data, acceleration of the rate at which this data must be consumed, and an increase in the diversity of sources of data. Memory system architectures and designs are perhaps most affected by these changes in computing applications. The disruptive trends resulting from these new application spaces lead to significant capacity, power, and cost pressures on computing systems. These trends will lead to changes in traditional memory technologies and memory systems and represent an opportunity of new memory technologies and organizations. Storage class memory is particularly suited to a significant set of these application spaces.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122960537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the amplitude of random telegraph noise 随机电报噪声的振幅
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-TSA.2012.6210145
K. Cheung, J. Campbell, S. Potbhare, A. Oates
{"title":"On the amplitude of random telegraph noise","authors":"K. Cheung, J. Campbell, S. Potbhare, A. Oates","doi":"10.1109/VLSI-TSA.2012.6210145","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210145","url":null,"abstract":"A simple physical model is developed to show that the “hole-in-the-inversion-layer” model for RTN is in fact correct. This simple model allows RTN amplitude for future devices to be predicted intuitively and quantitatively. The model provides additional incite into the physics of RTN in MOSFETs.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129619508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impact of thermal budget on dopant-segregated (DS) metal S/D gate-all-around (GAA) PFETs 热收支对掺杂剂偏析(DS)金属S/D栅极全能(GAA) pfet的影响
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-TSA.2012.6210131
K. Akarvardar, M. Rodgers, V. Kaushik, C. Johnson, I. Ok, K. Ang, H. Stamper, S. Bennett, D. Franca, M. Rao, S. Gausepohl, C. Hobbs, P. Kirsch, R. Jammy
{"title":"Impact of thermal budget on dopant-segregated (DS) metal S/D gate-all-around (GAA) PFETs","authors":"K. Akarvardar, M. Rodgers, V. Kaushik, C. Johnson, I. Ok, K. Ang, H. Stamper, S. Bennett, D. Franca, M. Rao, S. Gausepohl, C. Hobbs, P. Kirsch, R. Jammy","doi":"10.1109/VLSI-TSA.2012.6210131","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210131","url":null,"abstract":"Low temperature (T ≤ 480C after gate stack) DS Metal S/D GAA PFETs were fabricated and benchmarked to devices with S/D activation anneal (SDAA). It is shown that when DS implantation precedes gate spacer formation, devices without SDAA have higher peak G<sub>m</sub> and I<sub>Dsat</sub>, however also higher I<sub>off</sub> than their counterparts with SDAA. Fabricated low-thermal-budget GAA PFETs with TiN/HfO<sub>2</sub> gate and NiPtSi S/D achieve I<sub>Dsat</sub> = 0.8 mA/um and I<sub>on</sub>/I<sub>off</sub> >; 2000 for VGS = -1.5 V, V<sub>DS</sub> = -1 V, and 100 nm nanowire length.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130485583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thin-body FinFET as scalable low voltage transistor 作为可伸缩低压晶体管的薄体FinFET
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-TSA.2012.6210163
C. Hu
{"title":"Thin-body FinFET as scalable low voltage transistor","authors":"C. Hu","doi":"10.1109/VLSI-TSA.2012.6210163","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210163","url":null,"abstract":"FinFET provides needed relief to ICs from performance, power, and device variation predicaments. It also provides higher carrier mobility, especially at low voltage near the threshold voltage, giving promise to practical near-threshold circuits. Another new transistor conceived simultaneously with FinFET, UTB-SOI FET, is also entering production. Together they showed a new scaling path forward: scale the body thickness in proportion to gate length.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128878749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
III–V gate stack interface improvement to enable high mobility 11nm node CMOS III-V栅极堆叠接口改进，实现高迁移率11nm节点CMOS
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-TSA.2012.6210157
Y. T. Chen, J. Huang, J. Price, P. Lysaght, D. Veksler, C. Weiland, J. Woicik, G. Bersuker, R. Hill, J. Oh, P. Kirsch, R. Jammy, J. Lee
{"title":"III–V gate stack interface improvement to enable high mobility 11nm node CMOS","authors":"Y. T. Chen, J. Huang, J. Price, P. Lysaght, D. Veksler, C. Weiland, J. Woicik, G. Bersuker, R. Hill, J. Oh, P. Kirsch, R. Jammy, J. Lee","doi":"10.1109/VLSI-TSA.2012.6210157","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210157","url":null,"abstract":"We report significant improvements in the high-k/In<sub>0.53</sub>Ga<sub>0.47</sub>As interface quality by controlling atomic layer deposition (ALD) oxidizer chemistry. A step-by-step correlation between electrical data and chemical reactions at the high-k/InGaAs interface has been established using synchrotron photoemission. AsO<sub>x</sub>, GaO<sub>x</sub>, and In<sub>2</sub>O<sub>3</sub> formed during unintentional ALD surface oxidation and the increase of As-As bonds are responsible for degrading device quality. A better quality H<sub>2</sub>O-based high-k gate stack is evidenced by less capacitance-voltage (CV) dispersion (14% in ZrO<sub>2</sub>), smaller CV hysteresis (37% in Al<sub>2</sub>O<sub>3</sub> and 47% in ZrO<sub>2</sub>), fewer border traps (Q<sub>br</sub>) (96% in Al<sub>2</sub>O<sub>3</sub> and 25% in ZrO<sub>2</sub>), and lower mean interface traps density (D<sub>it</sub>) (91% in Al<sub>2</sub>O<sub>3</sub> and 29% in ZrO<sub>2</sub>). Improvements in I<sub>d</sub> and G<sub>m</sub> therefore have been achieved by replacing O<sub>3</sub> with H<sub>2</sub>O oxidizer. Our work suggests that H<sub>2</sub>O-based high-k is more promising than O<sub>3</sub>-based high-k. These results positively impact the industry's progress toward III-V CMOS at the 11nm node.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127824656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling and tuning the filament properties in RRAM metal oxide stacks for optimized stable cycling 模拟和调整RRAM金属氧化物堆中的灯丝特性，以优化稳定循环
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-TSA.2012.6210101
R. Degraeve, L. Goux, S. Clima, B. Govoreanu, Y. Chen, G. Kar, P. Rousse, G. Pourtois, D. Wouters, L. Altimime, M. Jurczak, G. Groeseneken, J. Kittl
{"title":"Modeling and tuning the filament properties in RRAM metal oxide stacks for optimized stable cycling","authors":"R. Degraeve, L. Goux, S. Clima, B. Govoreanu, Y. Chen, G. Kar, P. Rousse, G. Pourtois, D. Wouters, L. Altimime, M. Jurczak, G. Groeseneken, J. Kittl","doi":"10.1109/VLSI-TSA.2012.6210101","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210101","url":null,"abstract":"Forming current I<sub>form</sub> is a crucial parameter for stable cycling in a HfO<sub>2</sub> RRAM stack. (i) Too low I<sub>form</sub> results in constriction `elongation' for filament current reduction during reset, quickly leading to failure. (ii) Too high and unlimited I<sub>form</sub> leads to poor control of the filament nature expressed as a wide V<sub>0</sub>-distribution in the QPC model. (iii) In between, I<sub>form</sub> is directly correlated to the minimal achievable HRS current and a narrow, stable filament is formed which allows for device scaling as well as multi-level programming.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Nano carbon devices and applications 纳米碳器件及其应用
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-TSA.2012.6210117
K. Matsumoto, Y. Oho, K. Maehashi, T. Kamimura, K. Inoue, Y. Hayashi
{"title":"Nano carbon devices and applications","authors":"K. Matsumoto, Y. Oho, K. Maehashi, T. Kamimura, K. Inoue, Y. Hayashi","doi":"10.1109/VLSI-TSA.2012.6210117","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210117","url":null,"abstract":"In this paper, three kinds of devices and applications of nano carbon materials, i.e., carbon nanotube and graphene are introduced. 1) Using the feature of the nanostructure of carbon nanotube, quantum nano memory which can store the single charge one by one at the interface of the all arounded double stacked gate insulator was realized. 2) Only by modulating the gate bias, the particle nature and the wave nature of electron can be controlled, and Kondo resonance state was realized. 3) First selective bio sensor was realized using the aptamer modified graphene FET with high sensitivity.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"35 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120993814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical characterization and reliability investigations of Cu TSVs with wafer-level Cu/Sn-BCB hybrid bonding 晶圆级Cu/Sn-BCB杂化键合Cu tsv的电学特性及可靠性研究
Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI: 10.1109/VLSI-TSA.2012.6210175
Yao-Jen Chang, Cheng-Ta Ko, Z. Hsiao, Ting-Yang Yu, Y. -. Chen, W. Lo, Kuan-Neng Chen
{"title":"Electrical characterization and reliability investigations of Cu TSVs with wafer-level Cu/Sn-BCB hybrid bonding","authors":"Yao-Jen Chang, Cheng-Ta Ko, Z. Hsiao, Ting-Yang Yu, Y. -. Chen, W. Lo, Kuan-Neng Chen","doi":"10.1109/VLSI-TSA.2012.6210175","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2012.6210175","url":null,"abstract":"A wafer-level 3D integration structure with Cu TSVs based on Cu/Sn micro-bumps and BCB hybrid bonding is demonstrated. Kelvin structure and daisy chain design are adopted for electrical characterization and reliability evaluation. The results indicate the developed 3D integration scheme has excellent reliability and electrical stability.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"127 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121014366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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