PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology

Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI:10.1109/VLSI-TSA.2012.6210152

L. Song, Y. Liang, H. Onoda, C. W. Lai, T. Wallner, A. Pofelski, C. Gruensfelder, E. Josse, T. Okawa, J. Brown, R. Williams, J. Holt, J. W. Weijtmans, B. Greene, H. Utomo, S. Lee, D. Nair, Q. Zhang, C. Zhu, X. Wu, M. Sherony, Y. Lee, W. Henson, R. Divakaruni, E. Kaste

引用次数: 3

Abstract

The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.

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PMOSFET布局依赖于嵌入式SiGe源/漏极在POLY和STI边缘在32/28nm CMOS技术

PC-bounded或STI-bounded eSiGe诱导的eSiGe布局效应对器件性能产生影响，可变性增加。对于pc绑定的器件，性能下降可以解释为由于eSiGe体积减小和应力强度降低而导致的迁移率损失。对于sti -bound器件，由于eSiGe填充形态和器件重叠电容之间的强相互作用，性能下降有所不同。这一观察结果被eSiGe填充水平研究证实。与pc绑定的eSiGe相比，sti绑定的设备由于eSiGe过程而增加了变化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of Technical Program of 2012 VLSI Technology, System and Application

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