Impact of thermal budget on dopant-segregated (DS) metal S/D gate-all-around (GAA) PFETs

Abstract

Low temperature (T ≤ 480C after gate stack) DS Metal S/D GAA PFETs were fabricated and benchmarked to devices with S/D activation anneal (SDAA). It is shown that when DS implantation precedes gate spacer formation, devices without SDAA have higher peak G_m and I_Dsat, however also higher I_off than their counterparts with SDAA. Fabricated low-thermal-budget GAA PFETs with TiN/HfO₂ gate and NiPtSi S/D achieve I_Dsat = 0.8 mA/um and I_on/I_off >; 2000 for VGS = -1.5 V, V_DS = -1 V, and 100 nm nanowire length.