2016 IEEE International Conference on Rebooting Computing (ICRC)最新文献_第4页

Stochastic single flux quantum neuromorphic computing using magnetically tunable Josephson junctions 随机单通量量子神经形态计算利用磁可调谐约瑟夫森结

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738712

S. Russek, C. Donnelly, M. Schneider, B. Baek, M. Pufall, W. Rippard, P. Hopkins, P. Dresselhaus, S. Benz

引用次数: 23

Challenges for optical interconnect for beyond Moore's law computing 超摩尔定律计算对光互连的挑战

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738696

A. Lentine, C. DeRose

引用次数: 2

All-optical neuromorphic computing in optical networks of semiconductor lasers 半导体激光器光网络中的全光神经形态计算

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738705

D. Brunner, S. Reitzenstein, Ingo Fischer

引用次数: 9

Rethinking operating systems for rebooted computing 为重新启动的计算重新思考操作系统

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738695

Phil Laplante, D. Milojicic

{"title":"Rethinking operating systems for rebooted computing","authors":"Phil Laplante, D. Milojicic","doi":"10.1109/ICRC.2016.7738695","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738695","url":null,"abstract":"as the deceleration of processor scaling due to Moore's law accelerates research in new types of computing structures, the need arises for rethinking operating systems paradigms. Traditionally, an operating system is a layer between hardware and applications and its primary function is in managing hardware resources and providing a common abstraction to applications. How does this function apply, however, to new types of computing paradigms? Are operating systems even needed for these new structures? This paper revisits operating system functionality for new computing paradigms. The structure of these new computers is uncertain as there are many possibilities such as neuromorphic, bio-inspired, adiabatic, reversible, approximate, quantum, combinations of these and others unforeseen [1]. We do know, however, that whatever these new computers will be, there will be some need to manage their resources, to provide programming support, to partition, scale, and connect them and to deal with (partial) failure, along with other traditional operating system's functionality. There might also be some new functionality, such as creating abstract control loops, reasoning about precision, new ways of reconfiguring, and more. We strongly believe that even if traditional operating systems functionality evolves, that the need for operating systems will remain in the new era of computing.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122113598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A path toward ultra-low-energy computing 通往超低能耗计算的道路

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738677

E. Debenedictis, M. Frank, N. Ganesh, N. Anderson

引用次数: 16

Information-theoretic limits of algorithmic noise tolerance 算法噪声容忍度的信息理论限制

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738715

Daewon Seo, L. Varshney

引用次数: 7

Computing architecture to perform approximated simulated annealing for Ising models 对Ising模型进行近似模拟退火的计算架构

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738673

Takuya Okuyama, C. Yoshimura, Masato Hayashi, M. Yamaoka

{"title":"Computing architecture to perform approximated simulated annealing for Ising models","authors":"Takuya Okuyama, C. Yoshimura, Masato Hayashi, M. Yamaoka","doi":"10.1109/ICRC.2016.7738673","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738673","url":null,"abstract":"In the near future, the techniques to solve combinatorial optimization problems will become important in various fields and require large computing power. However, the performance growth of von Neumann architecture will slow down due to the end of semiconductor scaling. To resolve this problem, a computing architecture is proposed that maps the optimization problems to the ground state search of Ising models. The authors implemented the architecture, which finds the ground state by circuit operations inspired by SA, in CMOS circuits. The architecture adopts a modified algorithm using a majority function to simplify circuits. Though the power efficiency can be estimated to be 1800 times higher than that of a CPU, the modification deteriorates solution quality because it breaks the detailed balance condition. This paper presents a computing architecture that performs SA for Ising models approximately. The architecture satisfies the condition by utilizing the fact that the output of the majority voter circuit with stochastically processed inputs approximately behaves in accordance with the Glauber dynamics. Simulations demonstrate that solution quality of the proposed architecture is as good as that of SA. Our architecture can be power-efficient because the rate of increase in the number of transistors is less than 42%.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127342653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Erasing logic-memory boundaries in superconductor electronics 在超导体电子学中消除逻辑存储器边界

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738711

V. Semenov

{"title":"Erasing logic-memory boundaries in superconductor electronics","authors":"V. Semenov","doi":"10.1109/ICRC.2016.7738711","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738711","url":null,"abstract":"Superconductor electronics holds records for clock frequency and energy efficiency at the chip level, and is also projected to large systems that can absorb the cooling overhead. These advantages have nevertheless only managed to give this technology a back seat to CMOS digital circuits, which offer orders of magnitude more complexity. Furthermore, pursuing the CMOS paradigm with superconductor circuits would bring their clock frequency down to that of CMOS circuits. This makes superconductor technology much more open to risky innovations and even for paradigm changes. In the paper we point out that both (speed and energy efficiency) advantages of superconductor electronics could be preserved due to a unique composition of memory and logic functions of RSFQ cells. We propose to reorganize the original RSFQ cells into a new family of Memory And loGIC (MAGIC) gate/register objects that run arithmetic calculations as well as store results. The new MAGIC objects eliminate the time and energy overheads associated with the conventional transfer of computed data to memory by essentially reducing the transfer distance to zero. The new objects could serve as building blocks for distributed MAGIC-compatible architectures, differing from CMOS-like register files by processing as well as storing data. A simple Logic Unit (LU) would be sufficient to control the MAGIC registers, because the registers would provide most of the arithmetic functions and separate ALUs would not be needed. The reduction of the data exchange between logic and memory units leads to additional energy saving. Factorization of large integers is presented as an example illustrating the speed and density advantages of the new approach. The end result will be a superior technology which offers a combination of performance and energy efficiency unattainable by existing technologies or their possible extensions.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128691612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Accelerating Discrete Fourier Transforms with dot-product engine 用点积引擎加速离散傅里叶变换

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738682

Miao Hu, J. Strachan

引用次数: 8

A Mini-MIPS microprocessor for adiabatic computing 用于绝热计算的Mini-MIPS微处理器

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738678

César O. Campos-Aguillón, Rene Celis-Cordova, Ismo Hänninen, C. Lent, A. Orlov, G. Snider

{"title":"A Mini-MIPS microprocessor for adiabatic computing","authors":"César O. Campos-Aguillón, Rene Celis-Cordova, Ismo Hänninen, C. Lent, A. Orlov, G. Snider","doi":"10.1109/ICRC.2016.7738678","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738678","url":null,"abstract":"This paper examines adiabatic logic for computation, and presents a design for a MIPS processor implemented in CMOS. Adiabatic reversible logic was examined in the 1980s and 1990s but in that era power dissipation was a secondary concern, and the trade-off of reduced computational speed for reduced power was deemed unacceptable. Now, power dissipation and the associated heat are the major obstacles limiting progress in integrated circuits, particularly processors. In modern processors trading performance for reduced power dissipation is already done using techniques such as multi-core and dark silicon, so adiabatic logic may now be an attractive approach. To evaluate the adiabatic approach, this paper uses the figure of merit of the product of switching energy, delay time, and area (EDA). Using this figure of merit, adiabatic logic is shown to be advantageous when additional constraints are considered, such as maximum allowed power density. As a proof of concept circuit, a simplified MIPS microprocessor was designed using adiabatic logic based on split-rail charge recovery logic and Bennett clocking. New design and verification tools were developed using structural Verilog and extensions of ModelSim to provide needed capabilities are not available in commercial packages. The design is implemented using a standard cell design.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133396825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11