2016 IEEE International Conference on Rebooting Computing (ICRC)最新文献

Designing reconfigurable large-scale deep learning systems using stochastic computing 利用随机计算设计可重构的大规模深度学习系统

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-11-08 DOI: 10.1109/ICRC.2016.7738685

Ao Ren, Zhe Li, Yanzhi Wang, Qinru Qiu, Bo Yuan

{"title":"Designing reconfigurable large-scale deep learning systems using stochastic computing","authors":"Ao Ren, Zhe Li, Yanzhi Wang, Qinru Qiu, Bo Yuan","doi":"10.1109/ICRC.2016.7738685","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738685","url":null,"abstract":"Deep Learning, as an important branch of machine learning and neural network, is playing an increasingly important role in a number of fields like computer vision, natural language processing, etc. However, large-scale deep learning systems mainly operate in high-performance server clusters, thus restricting the application extensions to personal or mobile devices. The solution proposed in this paper is taking advantage of the fantastic features of stochastic computing methods. Stochastic computing is a type of data representation and processing technique, which uses a binary bit stream to represent a probability number (by counting the number of ones in this bit stream). In the stochastic computing area, some key arithmetic operations such as additions or multiplications can be implemented with very simple components like AND gates or multiplexers, respectively. Thus it provides an immense design space for integrating a large amount of neurons and enabling fully parallel and scalable hardware implementations of large-scale deep learning systems. In this paper, we present a reconfigurable large-scale deep learning system based on stochastic computing technologies, including the design of the neuron, the convolution function, the back-propagation function and some other basic operations. And the network-on-chip technique is also proposed in this paper to achieve the goal of implementing a large-scale hardware system. Our experiments validate the functionality of reconfigurable deep learning systems using stochastic computing, and demonstrate that when the bit streams are set to be 8192 bits, classification of MNIST digits by stochastic computing can perform as low error rate as that by normal arithmetic operations.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123400815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Bayesian sensor fusion with fast and low power stochastic circuits 基于快速低功耗随机电路的贝叶斯传感器融合

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-17 DOI: 10.1109/ICRC.2016.7738672

Alexandre Coninx, P. Bessière, E. Mazer, J. Droulez, R. Laurent, Awais Aslam, J. Lobo

{"title":"Bayesian sensor fusion with fast and low power stochastic circuits","authors":"Alexandre Coninx, P. Bessière, E. Mazer, J. Droulez, R. Laurent, Awais Aslam, J. Lobo","doi":"10.1109/ICRC.2016.7738672","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738672","url":null,"abstract":"As the physical limits of Moore's law are being reached, a research effort is launched to achieve further performance improvements by exploring computation paradigms departing from standard approaches. The BAMBI project (Bottom-up Approaches to Machines dedicated to Bayesian Inference) aims at developing hardware dedicated to probabilistic computation, which extends logic computation realised by boolean gates in current computer chips. Such probabilistic computing devices would allow to solve faster and at a lower energy cost a wide range of Artificial Intelligence applications, especially when decisions need to be taken from incomplete data in an uncertain environment. This paper describes an architecture where very simple operators compute on a time coding of probability values as stochastic signals. Simulation tests and a reconfigurable logic hardware implementation demonstrated the feasibility and performances of the proposed inference machine. Hardware results show this architecture can quickly solve Bayesian sensor fusion problems and is very efficient in terms of energy consumption.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133047576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Accelerating machine learning with Non-Volatile Memory: Exploring device and circuit tradeoffs 用非易失性存储器加速机器学习:探索器件和电路的权衡

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738684

Alessandro Fumarola, P. Narayanan, Lucas L. Sanches, Severin Sidler, Junwoo Jang, Kibong Moon, R. Shelby, H. Hwang, G. Burr

引用次数: 29

Neuromorphic mixed-signal circuitry for Asynchronous Pulse Processing 异步脉冲处理的神经形态混合信号电路

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738686

P. Petre, J. Cruz-Albrecht

引用次数: 4

Parallel data processing with Magnonic Holographic Co-Processor 磁振子全息协处理器并行数据处理

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738708

M. Balynsky, D. Gutierrez, H. Chiang, A. Khitun, A. Kozhevnikov, Y. Khivintsev, G. Dudko, Y. Filimonov

引用次数: 1

Reducing data movement with approximate computing techniques 使用近似计算技术减少数据移动

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738675

S. Crago, D. Yeung

引用次数: 2

Brain inspired photonic motif networks 受大脑启发的光子基序网络

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738706

F. Monifi, S. Shahin, F. Vallini, Y. Fainman, M. Rabinovich

引用次数: 0

Processor-in-memory support for artificial neural networks 对人工神经网络的内存处理器支持

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738697

J. Schabel, Lee Baker, Sumon Dey, Weifu Li, P. Franzon

{"title":"Processor-in-memory support for artificial neural networks","authors":"J. Schabel, Lee Baker, Sumon Dey, Weifu Li, P. Franzon","doi":"10.1109/ICRC.2016.7738697","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738697","url":null,"abstract":"Hardware acceleration of artificial neural network (ANN) processing has potential for supporting applications benefiting from real time and low power operation, such as autonomous vehicles, robotics, recognition and data mining. Most interest in ANNs targets acceleration of deep multi-layered ANNs that can require days of offline training to converge on a desired network behavior. Interest has grown in ANNs capable of supporting unsupervised training, where networks can learn new information from unlabeled data dynamically without the need for offline training. These ANNs require large memories with bandwidths much higher than supported in modern GPGPUs. Custom hardware acceleration and memory co-design holds the potential to provide real-time performance in cases where the performance requirements cannot be met by modern GPGPUs. This work presents a custom processor solution to accelerate two hetero-associative memories (Sparsey and HTM) capable of unsupervised and one-hot learning. This custom processor is implemented as an expandable ASIP built upon a configurable SIMD engine for exploiting parallelism. Functional specialization is implemented utilizing processor-in-memory techniques, which results in up to a 20× speedup and a 2000× reduction in energy per frame compared to a software implementation operating on a dataset for recognition of human actions.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124254870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A recurrent crossbar of memristive nanodevices implements online novelty detection 忆阻纳米器件的循环交叉棒实现了在线新颖性检测

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738689

C. Bennett, D. Querlioz, Jacques-Olivier Klein

引用次数: 0

Digital neuromorphic design of a Liquid State Machine for real-time processing 实时处理的数字神经形态液体状态机设计

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738687

Anvesh Polepalli, Nicholas Soures, D. Kudithipudi

{"title":"Digital neuromorphic design of a Liquid State Machine for real-time processing","authors":"Anvesh Polepalli, Nicholas Soures, D. Kudithipudi","doi":"10.1109/ICRC.2016.7738687","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738687","url":null,"abstract":"The Liquid State Machine (LSM) is a form of reservoir computing which emulates the brains capability of processing spatio-temporal data. This type of network generates highly descriptive responses to continuous input streams. The response is then used to extract information about the input stream. A single LSM network can be used as a generic intelligent processor that processes different streams of data (or) on same stream of data to extract different features. The LSM has been shown to perform well in tasks dependent on a systems behavior through time. The LSM's intrinsic memory and its reduced training complexity make it a suitable choice for hardware implementations for spatio-temporal applications. Existing behavioral models of LSM cannot process real time data due to their hardware complexity or inability to deal with real-time data or both. The proposed model focuses on a simple liquid design that exploits spatial locality and is capable of processing real time data. The model is evaluated for EEG seizure detection with an accuracy of 84.2% and for user identification based on walking pattern with an accuracy of 98.4%.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126739690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18