2016 IEEE International Conference on Rebooting Computing (ICRC)最新文献_第2页

Towards Logic-In-Memory circuits using 3D-integrated Nanomagnetic logic 使用3d集成纳米磁逻辑的内存逻辑电路

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738700

F. Riente, G. Ziemys, G. Turvani, D. Schmitt-Landsiedel, S. B. Gamm, M. Graziano

{"title":"Towards Logic-In-Memory circuits using 3D-integrated Nanomagnetic logic","authors":"F. Riente, G. Ziemys, G. Turvani, D. Schmitt-Landsiedel, S. B. Gamm, M. Graziano","doi":"10.1109/ICRC.2016.7738700","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738700","url":null,"abstract":"Perpendicular Nanomagnetic logic (pNML) is one emerging beyond-CMOS technology listed in the ITRS roadmap for next-generation computing due to its non-volatility, monolithic 3D-Integration, small size scalability and low power consumption. Here, we demonstrate the feasibility of a monolithic 3D pNML circuit, which is capable of integrating both memory and logic onto the same device on different layers by exploiting the novel Logic-In-Memory (LIM) concept. The LIM can be exploited by placing magnetic memory elements (registers) in a memory layer, which is located monolithically just below the performing logic plane and interconnected by pure-magnetic vias. In particular, the nonvolatile magnetization state of the bistable, nanoscaled magnets with perpendicular magnetic anisotropy is exploited to build a magnetic D flip-flop. This basic memory element is then used to build a more compact and a more power efficient N-bit parallel-in parallel-out register. Indeed, the presented magnetic flip-flop implementation is two orders of magnitude more compact when compared to the 32nm CMOS version. The approach has been studied by considering the implementation of an accumulator (adder plus memory) as case study. Moreover, we compare the occupied area of a N-bit accumulator with the 45nm and 28nm CMOS technology nodes. This novel concept enables the storage of information locally on the computing chip, saving area and employing the strengths of pNML for next-generation, memory-intensive computing tasks.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Opportunities in physical computing driven by analog realization 由模拟实现驱动的物理计算机会

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738680

J. Hasler

引用次数: 28

Energy efficiency limits of logic and memory 逻辑和内存的能效限制

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738676

S. Agarwal, Jeanine E. Cook, E. Debenedictis, M. Frank, G. Cauwenberghs, S. Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, T. Conte

引用次数: 3

A functional architecture for scalable quantum computing 可扩展量子计算的功能架构

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738703

E. Sete, W. Zeng, C. Rigetti

引用次数: 71

Approximate computing: Challenges and opportunities 近似计算:挑战与机遇

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738674

A. Agrawal, Jungwook Choi, K. Gopalakrishnan, Suyog Gupta, R. Nair, Jinwook Oh, D. Prener, Sunil Shukla, V. Srinivasan, Zehra Sura

{"title":"Approximate computing: Challenges and opportunities","authors":"A. Agrawal, Jungwook Choi, K. Gopalakrishnan, Suyog Gupta, R. Nair, Jinwook Oh, D. Prener, Sunil Shukla, V. Srinivasan, Zehra Sura","doi":"10.1109/ICRC.2016.7738674","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738674","url":null,"abstract":"Approximate computing is gaining traction as a computing paradigm for data analytics and cognitive applications that aim to extract deep insight from vast quantities of data. In this paper, we demonstrate that multiple approximation techniques can be applied to applications in these domains and can be further combined together to compound their benefits. In assessing the potential of approximation in these applications, we took the liberty of changing multiple layers of the system stack: architecture, programming model, and algorithms. Across a set of applications spanning the domains of DSP, robotics, and machine learning, we show that hot loops in the applications can be perforated by an average of 50% with proportional reduction in execution time, while still producing acceptable quality of results. In addition, the width of the data used in the computation can be reduced to 10-16 bits from the currently common 32/64 bits with potential for significant performance and energy benefits. For parallel applications we reduced execution time by 50% using relaxed synchronization mechanisms. Finally, our results also demonstrate that benefits compounded when these techniques are applied concurrently. Our results across different applications demonstrate that approximate computing is a widely applicable paradigm with potential for compounded benefits from applying multiple techniques across the system stack. In order to exploit these benefits it is essential to re-think multiple layers of the system stack to embrace approximations ground-up and to design tightly integrated approximate accelerators. Doing so will enable moving the applications into a world in which the architecture, programming model, and even the algorithms used to implement the application are all fundamentally designed for approximate computing.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126455400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 78

Spiking network algorithms for scientific computing 科学计算的峰值网络算法

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738681

William M. Severa, Ojas D. Parekh, Kristofor D. Carlson, C. James, J. Aimone

引用次数: 26

Hyperdimensional biosignal processing: A case study for EMG-based hand gesture recognition 超维生物信号处理:基于肌电图的手势识别案例研究

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738683

Abbas Rahimi, S. Benatti, P. Kanerva, L. Benini, J. Rabaey

{"title":"Hyperdimensional biosignal processing: A case study for EMG-based hand gesture recognition","authors":"Abbas Rahimi, S. Benatti, P. Kanerva, L. Benini, J. Rabaey","doi":"10.1109/ICRC.2016.7738683","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738683","url":null,"abstract":"The mathematical properties of high-dimensional spaces seem remarkably suited for describing behaviors produces by brains. Brain-inspired hyperdimensional computing (HDC) explores the emulation of cognition by computing with hypervectors as an alternative to computing with numbers. Hypervectors are high-dimensional, holographic, and (pseudo)random with independent and identically distributed (i.i.d.) components. These features provide an opportunity for energy-efficient computing applied to cyberbiological and cybernetic systems. We describe the use of HDC in a smart prosthetic application, namely hand gesture recognition from a stream of Electromyography (EMG) signals. Our algorithm encodes a stream of analog EMG signals that are simultaneously generated from four channels to a single hypervector. The proposed encoding effectively captures spatial and temporal relations across and within the channels to represent a gesture. This HDC encoder achieves a high level of classification accuracy (97.8%) with only 1/3 the training data required by state-of-the-art SVM on the same task. HDC exhibits fast and accurate learning explicitly allowing online and continuous learning. We further enhance the encoder to adaptively mitigate the effect of gesture-timing uncertainties across different subjects endogenously; further, the encoder inherently maintains the same accuracy when there is up to 30% overlapping between two consecutive gestures in a classification window.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132850545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 137

Neuromorphic computing with integrated photonics and superconductors 集成光子学和超导体的神经形态计算

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738694

J. Shainline, S. Buckley, R. Mirin, S. Nam

引用次数: 4

Technology considerations for neuromorphic computing 神经形态计算的技术考虑

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738688

D. Mountain

引用次数: 1

Computationally-redundant energy-efficient processing for y'all (CREEPY) 计算冗余节能处理(毛骨悚然)

2016 IEEE International Conference on Rebooting Computing (ICRC) Pub Date : 2016-10-01 DOI: 10.1109/ICRC.2016.7738714

Bobin Deng, S. Srikanth, Eric R. Hein, Paul G. Rabbat, T. Conte, E. Debenedictis, Jeanine E. Cook

{"title":"Computationally-redundant energy-efficient processing for y'all (CREEPY)","authors":"Bobin Deng, S. Srikanth, Eric R. Hein, Paul G. Rabbat, T. Conte, E. Debenedictis, Jeanine E. Cook","doi":"10.1109/ICRC.2016.7738714","DOIUrl":"https://doi.org/10.1109/ICRC.2016.7738714","url":null,"abstract":"Dennard scaling has ended. Lowering the voltage supply (Vdd) to sub volt levels causes intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable as a means to lower the power required by a processor core. However, if it were possible to recover the occasional losses due to lower Vdd in an efficient manner, one could effectively lower power. In other words, by deploying the right amount and kind of redundancy, we can strike a balance between overhead incurred in achieving reliability and savings realized by permitting lower Vdd. One promising approach is the Redundant Residue Number System (RRNS) representation. Unlike other error correcting codes, RRNS has the important property of being closed under addition, subtraction and multiplication. Thus enabling correction of errors caused due to both faulty storage and compute units. Furthermore, the incorporated approach uses a fraction of the overhead and is more efficient when compared to the conventional technique used for compute-reliability. In this article, we provide an overview of the architecture of a CREEPY core that leverages this property of RRNS and discuss associated algorithms such as error detection/correction, arithmetic overflow detection and signed number representation. Finally, we demonstrate the usability of such a computer by quantifying a performance-reliability trade-off and provide a lower bound measure of tolerable input signal energy at a gate, while still maintaining reliability.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131116578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7