{"title":"集成光子学和超导体的神经形态计算","authors":"J. Shainline, S. Buckley, R. Mirin, S. Nam","doi":"10.1109/ICRC.2016.7738694","DOIUrl":null,"url":null,"abstract":"We present a hardware platform combining integrated photonics with superconducting electronics for large-scale neuromorphic computing. Semiconducting few-photon light-emitting diodes work in conjunction with superconducting-nanowire single-photon detectors to behave as spiking neurons. These neurons are connected through a network of waveguides, and variable weights of connection can be implemented using several approaches. These processing units can operate at 20 MHz with fully asynchronous activity, light-speed-limited latency, and power densities on the order of 1 mW/cm2. The processing units achieve an energy efficiency of 20 aJ/synapse event, an improvement of six orders of magnitude over recent CMOS demonstrations [1]. We present calculations showing this approach could scale to interconnectivity near that of the human brain, and could surpass the brain in speed and efficiency.","PeriodicalId":387008,"journal":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Neuromorphic computing with integrated photonics and superconductors\",\"authors\":\"J. Shainline, S. Buckley, R. Mirin, S. Nam\",\"doi\":\"10.1109/ICRC.2016.7738694\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a hardware platform combining integrated photonics with superconducting electronics for large-scale neuromorphic computing. Semiconducting few-photon light-emitting diodes work in conjunction with superconducting-nanowire single-photon detectors to behave as spiking neurons. These neurons are connected through a network of waveguides, and variable weights of connection can be implemented using several approaches. These processing units can operate at 20 MHz with fully asynchronous activity, light-speed-limited latency, and power densities on the order of 1 mW/cm2. The processing units achieve an energy efficiency of 20 aJ/synapse event, an improvement of six orders of magnitude over recent CMOS demonstrations [1]. We present calculations showing this approach could scale to interconnectivity near that of the human brain, and could surpass the brain in speed and efficiency.\",\"PeriodicalId\":387008,\"journal\":{\"name\":\"2016 IEEE International Conference on Rebooting Computing (ICRC)\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Conference on Rebooting Computing (ICRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICRC.2016.7738694\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Conference on Rebooting Computing (ICRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICRC.2016.7738694","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Neuromorphic computing with integrated photonics and superconductors
We present a hardware platform combining integrated photonics with superconducting electronics for large-scale neuromorphic computing. Semiconducting few-photon light-emitting diodes work in conjunction with superconducting-nanowire single-photon detectors to behave as spiking neurons. These neurons are connected through a network of waveguides, and variable weights of connection can be implemented using several approaches. These processing units can operate at 20 MHz with fully asynchronous activity, light-speed-limited latency, and power densities on the order of 1 mW/cm2. The processing units achieve an energy efficiency of 20 aJ/synapse event, an improvement of six orders of magnitude over recent CMOS demonstrations [1]. We present calculations showing this approach could scale to interconnectivity near that of the human brain, and could surpass the brain in speed and efficiency.