Towards Logic-In-Memory circuits using 3D-integrated Nanomagnetic logic

Abstract

Perpendicular Nanomagnetic logic (pNML) is one emerging beyond-CMOS technology listed in the ITRS roadmap for next-generation computing due to its non-volatility, monolithic 3D-Integration, small size scalability and low power consumption. Here, we demonstrate the feasibility of a monolithic 3D pNML circuit, which is capable of integrating both memory and logic onto the same device on different layers by exploiting the novel Logic-In-Memory (LIM) concept. The LIM can be exploited by placing magnetic memory elements (registers) in a memory layer, which is located monolithically just below the performing logic plane and interconnected by pure-magnetic vias. In particular, the nonvolatile magnetization state of the bistable, nanoscaled magnets with perpendicular magnetic anisotropy is exploited to build a magnetic D flip-flop. This basic memory element is then used to build a more compact and a more power efficient N-bit parallel-in parallel-out register. Indeed, the presented magnetic flip-flop implementation is two orders of magnitude more compact when compared to the 32nm CMOS version. The approach has been studied by considering the implementation of an accumulator (adder plus memory) as case study. Moreover, we compare the occupied area of a N-bit accumulator with the 45nm and 28nm CMOS technology nodes. This novel concept enables the storage of information locally on the computing chip, saving area and employing the strengths of pNML for next-generation, memory-intensive computing tasks.