A Mini-MIPS microprocessor for adiabatic computing

Abstract

This paper examines adiabatic logic for computation, and presents a design for a MIPS processor implemented in CMOS. Adiabatic reversible logic was examined in the 1980s and 1990s but in that era power dissipation was a secondary concern, and the trade-off of reduced computational speed for reduced power was deemed unacceptable. Now, power dissipation and the associated heat are the major obstacles limiting progress in integrated circuits, particularly processors. In modern processors trading performance for reduced power dissipation is already done using techniques such as multi-core and dark silicon, so adiabatic logic may now be an attractive approach. To evaluate the adiabatic approach, this paper uses the figure of merit of the product of switching energy, delay time, and area (EDA). Using this figure of merit, adiabatic logic is shown to be advantageous when additional constraints are considered, such as maximum allowed power density. As a proof of concept circuit, a simplified MIPS microprocessor was designed using adiabatic logic based on split-rail charge recovery logic and Bennett clocking. New design and verification tools were developed using structural Verilog and extensions of ModelSim to provide needed capabilities are not available in commercial packages. The design is implemented using a standard cell design.