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2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)最新文献

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Design of an E-band Doherty Power amplifier e波段Doherty功率放大器的设计
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-08-08 DOI: 10.1109/PRIME.2018.8430350
M. Najmussadat, Raju Ahamed, D. Parveg, M. Varonen, K. Halonen
{"title":"Design of an E-band Doherty Power amplifier","authors":"M. Najmussadat, Raju Ahamed, D. Parveg, M. Varonen, K. Halonen","doi":"10.1109/PRIME.2018.8430350","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430350","url":null,"abstract":"This paper demonstrates the design of an E-band Doherty power amplifier (PA) based in an 130nm SiGe BiCMOS process. This design includes main and auxiliary amplifiers, lange coupler and a pre-amplifier. The designed power amplifier exhibits a saturated output power of 14.4 dBm and output referred P1dB of 11.7 dBm. The peak power added efficiency (PAE) of this amplifier is 19.2%. This PA shows PAE of 17% at P1dB and 11.6% at 6-dB output power back off. The peak power gain of this Doherty PA is 23 dB at 75 GHz with a 3-dB bandwidth from 60 to 80 GHz. The designed Doherty PA consumes DC power of 52 mW with a chip area of 900 μm × 800 μm without RF pads.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134492068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ka-/V-band self-biased LNAs in 70 nm GaAs/InGaAs Technology 70nm GaAs/InGaAs技术中的Ka / v波段自偏置LNAs
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-02 DOI: 10.1109/PRIME.2018.8430364
G. Polli, M. Vittori, W. Ciccognani, S. Colangeli, F. Costanzo, A. Salvucci, E. Limiti
{"title":"Ka-/V-band self-biased LNAs in 70 nm GaAs/InGaAs Technology","authors":"G. Polli, M. Vittori, W. Ciccognani, S. Colangeli, F. Costanzo, A. Salvucci, E. Limiti","doi":"10.1109/PRIME.2018.8430364","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430364","url":null,"abstract":"In this paper, two LNAs, designed to operate in Ka and V bands, and realized in a 70 nm GaAs/InGaAs technology, are presented. Both amplifiers have a 2-stage structure featured by source feedback and self-biasing networks to improve noise performance and to simplify the external circuitry, respectively. Total area occupation of the realized MMICs is 3x1.2 mm2 and 3x1 mm2. The Ka-band amplifier exhibits a noise figure lower than 1.5 dB over 27–31.5 GHz and a gain between 16 dB and 18 dB. The V-band LNA has a 1.7 dB noise figure in the 4751 GHz band, with an associated gain between 14.5 dB and 15.5 dB.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133576055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
System Level simulation framework for the ASICs development of a novel particle physics detector 一种新型粒子物理探测器专用集成电路的系统级仿真框架
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430367
Alessandro Caratelli, S. Scarfi, D. Ceresa, K. Kloukinas, Y. Leblebici
{"title":"System Level simulation framework for the ASICs development of a novel particle physics detector","authors":"Alessandro Caratelli, S. Scarfi, D. Ceresa, K. Kloukinas, Y. Leblebici","doi":"10.1109/PRIME.2018.8430367","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430367","url":null,"abstract":"The simulation of the passage of particles through matter using Monte Carlo methods is broadly used in the development of particle detectors for high energy physics experiments. To develop the readout electronics for the Compact Muon Solenoid (CMS) experiment at CERN, and to assist the design of the on-detector ASICs, a simulation framework was build capable to link the physics Monte Carlo simulations platforms with an industry standard EDA simulation tools. This contribution focuses on the implementation of the simulation framework based on the System Verilog language and the Universal Verification Methodology (UVM). The simulation results that guided the development of the ASICs and the choice of the final architecture are presented.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115451231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of a SIBO DC-DC Converter for AMOLED Display Driving 用于AMOLED显示器驱动的SIBO DC-DC变换器设计
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430357
F. Boera, A. Salimath, E. Bonizzoni, F. Maloberti
{"title":"Design of a SIBO DC-DC Converter for AMOLED Display Driving","authors":"F. Boera, A. Salimath, E. Bonizzoni, F. Maloberti","doi":"10.1109/PRIME.2018.8430357","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430357","url":null,"abstract":"This paper describes a Single Inductor Bipolar Outputs (SIBO) DC-DC converter for Active Matrix Organic Light Emitting Diode (AMOLED) displays. The circuit is able to generate with a single inductor both the positive and the negative voltage necessary to turn on the AMOLED pixels and does not require the addition of post-regulation techniques. The circuit works with an input battery voltage ranging from 2.4 V to 4.9 V, compliant with Li-Ion batteries, and is able to generate + 5 V and −6 V. The maximum output current delivered to the load is 0.6 A. The switching frequency is 2 MHz and the control loop has been implemented in Voltage Control Mode (VCM). The effectiveness of the single inductor based scheme has been verified at the behavioral level in Matlab-Simulink.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"568 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116204313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New Current Mode Wheatstone Bridge Topologies with Intrinsic Linearity 具有内在线性的新电流模式惠斯通电桥拓扑
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430363
L. Safari, G. Barile, V. Stornelli, G. Ferri, A. Leoni
{"title":"New Current Mode Wheatstone Bridge Topologies with Intrinsic Linearity","authors":"L. Safari, G. Barile, V. Stornelli, G. Ferri, A. Leoni","doi":"10.1109/PRIME.2018.8430363","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430363","url":null,"abstract":"In this paper two new topologies for current-mode Wheatstone bridge (CMWB) are presented. The circuits, unlike other CMWB topologies, are based on two second generation voltage conveyors (VCII) as basic building blocks and two nMOS transistors operating as variable resistor. The outputs of both circuits are intrinsically linear function of R. Compared to previously reported CMWB circuits, the proposed topologies offer several advantages. Firstly, they do not require any extra voltage buffer at output i.e., the produced output voltage can be directly used in practical applications. Secondly, they do not employ any passive resistor while there are multiple grounded and floating resistors in other CMWBs. Thirdly, they have the capability to electronically control the gain without a significant impact on consumed power. To confirm the proposed theory, PSpice simulation results using 0.35m CMOS technology parameters are presented.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128595279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
PRIME 2018 Welcome Page PRIME 2018欢迎页面
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/prime.2018.8430354
{"title":"PRIME 2018 Welcome Page","authors":"","doi":"10.1109/prime.2018.8430354","DOIUrl":"https://doi.org/10.1109/prime.2018.8430354","url":null,"abstract":"","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123933114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM 低功耗DRAM锁存电压检测放大器的检测良率分析
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430359
S. Kim, Byungkyu Song, Tae Woo Oh, Seong-ook Jung
{"title":"Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM","authors":"S. Kim, Byungkyu Song, Tae Woo Oh, Seong-ook Jung","doi":"10.1109/PRIME.2018.8430359","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430359","url":null,"abstract":"Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121475242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Bayesian indicator for Run-to-Run performance assessment in semiconductor manufacturing 半导体制造中运行到运行性能评估的贝叶斯指标
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430365
T. Korabi, G. Graton, E. E. Adel, M. Ouladsine, J. Pinaton
{"title":"A Bayesian indicator for Run-to-Run performance assessment in semiconductor manufacturing","authors":"T. Korabi, G. Graton, E. E. Adel, M. Ouladsine, J. Pinaton","doi":"10.1109/PRIME.2018.8430365","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430365","url":null,"abstract":"In this paper, Bayesian theory is used to build an indicator for Run-to-Run control. This indicator is used for assessing the performances of the regulation loops in a batch industry. The indicator is using four main inputs which are the output/target error, the dispersion of the output, the out of tolerance rate (oot) and the value of the industrial risk. The efficiency of the proposed Bayesian method has been tested on the deposition area of a semiconductor foundry.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125447208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low power Voice Activity Detector for portable applications 一种低功耗的便携式语音活动检测器
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430328
Gabriele Meoni, Luca Pilato, L. Fanucci
{"title":"A low power Voice Activity Detector for portable applications","authors":"Gabriele Meoni, Luca Pilato, L. Fanucci","doi":"10.1109/PRIME.2018.8430328","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430328","url":null,"abstract":"Voice Activity Detectors (VADs) are used to enhance performances and to reduce the activation rate of speech recognition and key-word spotting applications. The last aspect is crucial for portable applications because it allows to save energy, increasing battery life. During last decades, VADs have been realized through hardware solutions to increase their speed in processing and to reduce their power consumption. However, the hardware implementation often represents a limit on the choice of the features to use, limiting the performances on recognition. This paper shows a low-power and low-area serial logistic regression classffier which uses the frame-energy, the maximum absolute signal finite difference and the maximum absolute squared signal finite difference over a frame as features. The system has been implemented on IGLOO nano Field Programmable Gate Array (FPGA), leading to power consumption of 0.559 mW and offering acceptable performances for its use as a preprocessor for speech recognition systems or a more sophisticated software VAD.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115890916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Modeling and Simulation of Novel GaN-based Light Emitting Transistor for Display Applications 新型显示用氮化镓发光晶体管的建模与仿真
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430321
Sang Myung Lee, I. Yun
{"title":"Modeling and Simulation of Novel GaN-based Light Emitting Transistor for Display Applications","authors":"Sang Myung Lee, I. Yun","doi":"10.1109/PRIME.2018.8430321","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430321","url":null,"abstract":"For the research of next-generation displays, technology of shrink device size is the most attractive and important technology. It is possible to manufacture high- performance display products by using high integrated devices such as mobile application. However, there is a certain limitation to the downsizing technology. Therefore, new device synthesis techniques are becoming important. In this paper, we propose a device design that combines inorganic material based light- emitting diode (LED) and thin-film transistor (TFT). By integrating the LED and TFT devices into one region, it is possible to highly integrate the devices, which can greatly reduce the size of the entire device. To investigate a possibility of device implementation, technology computer-aided design (TCAD) simulation is used. After that, an optical and electrical characteristic of the device are analyzed. Finally, the light- emitting transistor (LET) is proposed.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131939606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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