Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM

Abstract

Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.