L. Safari, G. Barile, V. Stornelli, G. Ferri, A. Leoni
{"title":"具有内在线性的新电流模式惠斯通电桥拓扑","authors":"L. Safari, G. Barile, V. Stornelli, G. Ferri, A. Leoni","doi":"10.1109/PRIME.2018.8430363","DOIUrl":null,"url":null,"abstract":"In this paper two new topologies for current-mode Wheatstone bridge (CMWB) are presented. The circuits, unlike other CMWB topologies, are based on two second generation voltage conveyors (VCII) as basic building blocks and two nMOS transistors operating as variable resistor. The outputs of both circuits are intrinsically linear function of R. Compared to previously reported CMWB circuits, the proposed topologies offer several advantages. Firstly, they do not require any extra voltage buffer at output i.e., the produced output voltage can be directly used in practical applications. Secondly, they do not employ any passive resistor while there are multiple grounded and floating resistors in other CMWBs. Thirdly, they have the capability to electronically control the gain without a significant impact on consumed power. To confirm the proposed theory, PSpice simulation results using 0.35m CMOS technology parameters are presented.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"New Current Mode Wheatstone Bridge Topologies with Intrinsic Linearity\",\"authors\":\"L. Safari, G. Barile, V. Stornelli, G. Ferri, A. Leoni\",\"doi\":\"10.1109/PRIME.2018.8430363\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper two new topologies for current-mode Wheatstone bridge (CMWB) are presented. The circuits, unlike other CMWB topologies, are based on two second generation voltage conveyors (VCII) as basic building blocks and two nMOS transistors operating as variable resistor. The outputs of both circuits are intrinsically linear function of R. Compared to previously reported CMWB circuits, the proposed topologies offer several advantages. Firstly, they do not require any extra voltage buffer at output i.e., the produced output voltage can be directly used in practical applications. Secondly, they do not employ any passive resistor while there are multiple grounded and floating resistors in other CMWBs. Thirdly, they have the capability to electronically control the gain without a significant impact on consumed power. To confirm the proposed theory, PSpice simulation results using 0.35m CMOS technology parameters are presented.\",\"PeriodicalId\":384458,\"journal\":{\"name\":\"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PRIME.2018.8430363\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PRIME.2018.8430363","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
New Current Mode Wheatstone Bridge Topologies with Intrinsic Linearity
In this paper two new topologies for current-mode Wheatstone bridge (CMWB) are presented. The circuits, unlike other CMWB topologies, are based on two second generation voltage conveyors (VCII) as basic building blocks and two nMOS transistors operating as variable resistor. The outputs of both circuits are intrinsically linear function of R. Compared to previously reported CMWB circuits, the proposed topologies offer several advantages. Firstly, they do not require any extra voltage buffer at output i.e., the produced output voltage can be directly used in practical applications. Secondly, they do not employ any passive resistor while there are multiple grounded and floating resistors in other CMWBs. Thirdly, they have the capability to electronically control the gain without a significant impact on consumed power. To confirm the proposed theory, PSpice simulation results using 0.35m CMOS technology parameters are presented.