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2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)最新文献

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Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement 基于环面拓扑的柔性备核容错片上网络设计
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1145/3269983
P. V. Bhanu, P. Kulkarni, J. Soumya, Linga Reddy Cenkeramaddi, Henning Idsøe
{"title":"Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement","authors":"P. V. Bhanu, P. Kulkarni, J. Soumya, Linga Reddy Cenkeramaddi, Henning Idsøe","doi":"10.1145/3269983","DOIUrl":"https://doi.org/10.1145/3269983","url":null,"abstract":"The increase in the density of the IP cores being fabricated on a chip poses on-chip communication challenges and heat dissipation. To overcome these issues, Network-onChip (NoC) based communication architecture is introduced. In the nanoscale era NoCs are prone to faults which results in performance degradation and un-reliability. Hence efficient fault-tolerant methods are required to make the system reliable in contrast to diverse component failures. This paper presents a flexible spare core placement in torus topology based faulttolerant NoC design. The communications related to the failed core is taken care by selecting the best position for a spare core in the torus network. By considering this we propose a metaheuristic based Particle Swarm Optimization (PSO) technique to find suitable position for the spare core that minimizes the communication cost. We have experimented with several application benchmarks reported in the literature by varying the network size and by varying the fault-percentage in the network. The results show significant reduction in terms of communication cost compared to other approaches.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133278144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Enabling Secure Boot Functionality by Using Physical Unclonable Functions 通过使用物理不可克隆功能启用安全启动功能
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430370
Kai-Uwe Müller, Robin Ulrich, Alexander Stanitzki, R. Kokozinski
{"title":"Enabling Secure Boot Functionality by Using Physical Unclonable Functions","authors":"Kai-Uwe Müller, Robin Ulrich, Alexander Stanitzki, R. Kokozinski","doi":"10.1109/PRIME.2018.8430370","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430370","url":null,"abstract":"A firmware encryption for embedded devices can prevent the firmware from being read out to clone the device to a counterfeited one or to steal the intellectual property of the software developer. Also the integrity is ensured to hinder an attacker from manipulating the firmware to a malicious one. In this work, a cryptographic concept to implement a Secure Boot functionality using the intrinsic properties of a specific hardware device is shown. After describing the Physical Unclonable Function and the cipher used for the implementation, the key generation algorithm is explained. Further, the function of the crypto-module inside the system architecture and the secure boot sequence are described.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131866426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture 基于StrongARM架构的12.4fJ-FoM 4位闪存ADC
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430349
Abdullah S. Almansouri, Abdullah Alturki, H. Fariborzi, K. Salama, T. Al-Attar
{"title":"A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture","authors":"Abdullah S. Almansouri, Abdullah Alturki, H. Fariborzi, K. Salama, T. Al-Attar","doi":"10.1109/PRIME.2018.8430349","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430349","url":null,"abstract":"This work proposes an efficient 4-bit flash ADC based on the StrongARM comparator architecture. The proposed design eliminates the need for the resistive ladder by systematically modifying the sizing of the input differential pair of each comparator. As a consequence, the area and the power consumed within the ladder is eliminated. Furthermore, a Helpee StrongARM circuit is introduced which enables operation at an input voltage below the threshold voltage of the transistor. An enhanced 1-out-of-15 decoder converts the thermometer code from the StrongARM and the Helpee StrongARM comparators into a 1-out-of-n code. The proposed 4-bit flash ADC architecture, simulated in 90nm standard CMOS technology, consumes $292 {mu } mathrm {W}$ at 1.6 GHz sampling frequency, has an ENOB of 3.88 and FoM of 12.4 fJ/conv.step.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116152071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the Design of a Linear Delay Element for the Triggering Module at CERN LHC 欧洲核子研究中心大型强子对撞机触发模块线性延迟元件的设计
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430330
Jordan Lee Gauci, E. Gatt, O. Casha, G. Cataldo, I. Grech, J. Micallef
{"title":"On the Design of a Linear Delay Element for the Triggering Module at CERN LHC","authors":"Jordan Lee Gauci, E. Gatt, O. Casha, G. Cataldo, I. Grech, J. Micallef","doi":"10.1109/PRIME.2018.8430330","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430330","url":null,"abstract":"This paper presents an analytical model of a linear delay element circuit to be employed in the triggering module for the High Momentum Particle Identification Detector (HMPID) at the CERN Large Hadron Collider (LHC). The aim of the analytical model is to facilitate the design of the linear delay element circuit, while maximizing its linearity and delay range. The analytical model avoids the need of time consuming parametric sweeps on the aspect ratios of the various transistors of the delay element in order to optimize it. In addition, the analytical model can be used to predict the variation of the delay with the input tuning voltage. The proposed analytical model is verified via the simulation of the delay element circuit using the $0.18mu mathrm {m}$ X-FAB technology.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"120 26","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120820638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Increasing EM Robustness of Placement and Routing Solutions based on Layout-Driven Discretization 基于布局驱动离散化提高布局和路由解决方案的EM鲁棒性
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430323
Steve Bigalke, J. Lienig, T. Casper, S. Schöps
{"title":"Increasing EM Robustness of Placement and Routing Solutions based on Layout-Driven Discretization","authors":"Steve Bigalke, J. Lienig, T. Casper, S. Schöps","doi":"10.1109/PRIME.2018.8430323","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430323","url":null,"abstract":"Nowadays, electromigration (EM) is mainly addressed in the verification step. This is no longer possible due to the ever increasing number of EM failures in the future. An EM-aware physical synthesis could reduce the number of critical locations but the layout complexities prevent this from already being used. To solve this problem, we propose a novel method to discretize placement and routing solutions to enable a fast EM analysis. In addition, we suggest adjustments in the placement and routing step to enhance the EM robustness based on early analysis results. In contrast to the standard approach of running a numerical simulation outside the physical design step and after the synthesis, we perform most of the analysis steps within our placement and routing tools to consider the results; thus enabling early and specialized EM-robust solutions. Particularly, our methodology exploits layout structures to enable an efficient discretization inside the geometrical representations of synthesis tools. We demonstrate how to reduce the discretization effort significantly while achieving sufficient accuracy to improve EM robustness.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129428410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Sub-IV, 72 μW Stacked LNA-VCO for Wireless Sensor Network Applications 用于无线传感器网络的72 μW堆叠LNA-VCO
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430306
E. Kargaran, D. Manstretta, R. Castello
{"title":"A Sub-IV, 72 μW Stacked LNA-VCO for Wireless Sensor Network Applications","authors":"E. Kargaran, D. Manstretta, R. Castello","doi":"10.1109/PRIME.2018.8430306","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430306","url":null,"abstract":"Wireless sensor network (WSN) and Internet-of-Things (IoT) applications demand RF transceivers with extremely low power dissipation. An ultra-low power combined LNA-VCO is presented in this work with RF performance beyond the requirements of the intended application. The LNA current is lowered by factor of 12 in comparison with a standard common-gate LNA and it achieves impedance matching to 50 Ω thanks to current reuse combined with passive gain boosting. Stacking the VCO and the LNA voltage and power efficiency are improved even further. The power consumption of combined LNA-VCO is only 72 μW under a supply voltage of 0.9V. Simulation results in 40 nm CMOS technology at 2.4 GHz show and has a phase noise of -105.8 dBc/Hz at 1 MHz offset frequency, corresponding to a FoM of 194.1 dBc/Hz.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128677132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Novel Very Low Voltage Topology to implement MCML XOR Gates 一种实现MCML异或门的新颖极低电压拓扑
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430320
Davide Bellizia, G. Palumbo, G. Scotti, A. Trifiletti
{"title":"A Novel Very Low Voltage Topology to implement MCML XOR Gates","authors":"Davide Bellizia, G. Palumbo, G. Scotti, A. Trifiletti","doi":"10.1109/PRIME.2018.8430320","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430320","url":null,"abstract":"A new very low-voltage topology to implement MOS current mode logic (MCML) XOR gates is proposed in this paper. Instead of stacking several level oftransistors to implement a two inputs XOR gate, a p-type differential pair is used to steer the current in n-type differential pairs through current mirrors. The proposed topology allows to reduce the minimum supply voltage of MCML XOR gates while guaranteeing a fully current mode behavior as in the conventional XOR gate. The proposed topology has been compared against the conventional and triple tail MCML XOR gates. Simulation results referring to a $40mathrm {n}mathrm {m}$ CMOS technology for $V_{DD}=1mathrm {V}$ confirm that the XOR gate presented in this work exhibits a lower propagation delay than the previously published low voltage MCML XOR gate. Furthermore both theoretical analysis and simulation results in a $40mathrm {n}mathrm {m}$ process show that the proposed topology is able to work with a VDD as low as $0.~65mathrm {V}$ whereas state of the art topologies are not usable below $0.~8mathrm {V}.$","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131945969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fractional-Order Hartley Oscillator 分数阶哈特利振荡器
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430336
Agamyrat Agambayev, A. Kartci, Ali H. Hassan, N. Herencsar, H. Bağcı, K. Salama
{"title":"Fractional-Order Hartley Oscillator","authors":"Agamyrat Agambayev, A. Kartci, Ali H. Hassan, N. Herencsar, H. Bağcı, K. Salama","doi":"10.1109/PRIME.2018.8430336","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430336","url":null,"abstract":"A fractional-order capacitor (FOC) is developed using a Molybdenum disulfide ferroelectric polymer composite. The fabricated FOC exhibits constant phase over five decades between 100 Hz-10 MHz, which is the broadest operating frequency bandwidth reported so far for an FOC. Furthermore, a fractional-order Hartley oscillator is built using this FOC, and provide ten times higher oscillation frequency than the frequency of the conventional Hartley oscillator counterpart.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123748059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
PRIME 2018 Index PRIME 2018指数
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/prime.2018.8430347
{"title":"PRIME 2018 Index","authors":"","doi":"10.1109/prime.2018.8430347","DOIUrl":"https://doi.org/10.1109/prime.2018.8430347","url":null,"abstract":"","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133971667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Multi-level CMOS Switching Mode Amplifier for Mobile Communication Signals 一种新型的多电平CMOS开关模式移动通信信号放大器
2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI: 10.1109/PRIME.2018.8430318
R. Bieg, Martin Schmidt, M. Grozing, M. Berroth
{"title":"A Novel Multi-level CMOS Switching Mode Amplifier for Mobile Communication Signals","authors":"R. Bieg, Martin Schmidt, M. Grozing, M. Berroth","doi":"10.1109/PRIME.2018.8430318","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430318","url":null,"abstract":"This paper presents simulation results of a CMOS switching mode power amplifier (SA) in a 65nm technology with adjustable output voltage swing. The output stage is built in a stacked design to prevent dielectric breakdown of the transistors. Inverters at the top and bottom of the stack provide the supply voltage for the stack. The configuration offers a variable output voltage swing between one, two or three times the nominal transistor supply voltage. This paper demonstrates the advantages over a power amplifier with fixed output levels for signals with high peak to average output power ratio (PAPR).","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125631509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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