{"title":"PRIME 2018 Cover Page","authors":"","doi":"10.1109/prime.2018.8430309","DOIUrl":"https://doi.org/10.1109/prime.2018.8430309","url":null,"abstract":"","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121372381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving Deep Learning with a customizable GPU-like FPGA-based accelerator","authors":"M. Gagliardi, E. Fusella, A. Cilardo","doi":"10.1109/PRIME.2018.8430335","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430335","url":null,"abstract":"An ever increasing number of challenging appli- cations are being approached using Deep Learning, obtaining impressive results in a variety of different domains. However, state-of-the-art accuracy requires deep neural networks with a larger number of layers and a huge number of different filters with millions of weights. GPU- and FPGA-based architectures have been proposed as a possible solution for facing this enormous demand of computing resources. In this paper, we investigate the adoption of different architectural features, i.e., SIMD paradigm, multithreading, and non-coherent on-chip memory for Deep Learning oriented FPGA-based accelerator designs. Experimental results on a Xilinx Virtex-7 FPGA show that the SIMD paradigm and multithreading can lead to an improvement in the execution time up to $5{times }$and $3 . 5{times }$, respectively. A further enhancement up to $1 . 75{times }$can be obtained using a non-coherent on-chip memory.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126933101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Kampus, T. Rang, Daniel Knaller, C. Fleischhacker, Markus Korak, J. Kiss
{"title":"A fully differential, 200MHz, programmable gain, level-shifting, hybrid amplifier/power combiner/test buffer, using pre-distortion for enhanced linearity","authors":"V. Kampus, T. Rang, Daniel Knaller, C. Fleischhacker, Markus Korak, J. Kiss","doi":"10.1109/PRIME.2018.8430372","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430372","url":null,"abstract":"With the continuous advancement of standards in high-end telecommunication systems, requirements for analog circuitry have become ever more demanding. The new standards not only want to support better modulation schemes, demanding less noise with higher linearity, but also require increased bandwidth from analog circuitry. This paper describes a fully differential, programmable gain, baseband power combiner with a bandwidth of 200MHz, using pre-distortion for extra linearity, that offers also level-shifting and test buffer functionalities. The pre-distortion allows the improvement of linearity in the amplifiers AB stage, what otherwise would be a limiting factor in rail-to-rail swing operations and lowering the maximum throughput.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132670441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Alireza Mesri, M. Sampietro, Andre B. Cunha, G. Ferrari, Ø. Martinsen
{"title":"A Laser Diode-Based Wireless Optogenetic Headstage","authors":"Alireza Mesri, M. Sampietro, Andre B. Cunha, G. Ferrari, Ø. Martinsen","doi":"10.1109/PRIME.2018.8430348","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430348","url":null,"abstract":"A power efficient, battery powered optogenetic headstage for doing in-vivo experiments with freely moving genetically modified animals is presented. The proposed system is designed with commercial off-the-shelf components, and is based on a Bluetooth Low Energy (BLE) System-on-Chip (SoC) with an integrated antenna and a programmable ARM Cortex-M3 microprocessor core able to control the circuit. The optical signal is generated using a compact laser diode (LD) suitable for a wearable headstage. LD produces light in a highly concentrated way considerably improving the LD-optical fiber coupling efficiency. The proposed optogenetic system is shown to provide 120 mW/mm2 at the fiber tip with a current consumption of 60mA, considerably lower than LED-based systems. The system is remotely controlled by a smartphone app where the user can define optical stimulations patterns settings (optical power, frequency, duty cycle, etc.). It is also powerful enough to be ready to house additional optogenetics functionalities, like electrochemical sensing of the cell response, without significant modifications, thus being the basis of an integrated optogenetic platform.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131174243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hoda Fares, L. Seminara, H. Chible, S. Došen, M. Valle
{"title":"Multi-Channel Electrotactile Stimulation System for Touch Substitution: A Case Study","authors":"Hoda Fares, L. Seminara, H. Chible, S. Došen, M. Valle","doi":"10.1109/PRIME.2018.8430345","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430345","url":null,"abstract":"Reconstructing the sense of touch in prosthetics is a long-standing research challenge. To this aim, the prosthesis can be supplied with sensory arrays to measure the tactile interaction with the environment. In addition, a reliable feedback system is required to code and transmit the measured somatosensory information to the residual limb. This paper presents a multichannel electrotactile stimulation interface. Two coding schemes (mixed and uniform coding) were tested to assess the ability of the subject to localize the stimulation (identify the active pad). The outcome measures were position recognition and frequency discrimination. Our preliminary results show high accuracies in discriminating different frequency levels, i.e., 80% for low-level frequencies and 87% for high-level frequencies. In addition, the mixed coding has substantially improved the spatial localization. These are important insights regarding the development of multichannel sensing and stimulation systems for feedback in prosthetics.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114273231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-Stage Complex Notch Filtering for Interference Detection and Mitigation to Improve the Acquisition Performance of GPS","authors":"Syed Waqas Arif, Adem Coskun, I. Kale","doi":"10.1109/PRIME.2018.8430324","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430324","url":null,"abstract":"Continuous Wave Interferences (CWIs) can degrade the accuracy of a Global Positioning System (GPS) receiver and moreover it can completely deteriorate receiver’s normal operation. In this paper a low-cost anti-jamming system design is presented for the mitigation and detection of CWIs for GPS receivers. The anti-jamming system comprises of parameterizable Complex Adaptive Notch Filter (CANF) module which is able to detect and excise single or multiple CWIs. The CANF module is composed of afirst, second and third order infinite-impulse response filter with an Auto-Regressive Moving Averager structure. The proposed CANF detects the existence of the CWI and estimates JNR level of incoming signal by using the statistical value of the adaptive parameter b0. The impact of the CANF module on the acquisition is analyzed. Moreover, a simple and innovative system level model is proposed which can utilize each CANF efficiently with threshold setting of JNR estimation within the adaptation block. Threshold setting parameters provide trade-off between effective excision of CWI, order of the filter and power consumption. This results in a parameterizable CANF module and provide effective solution for the mitigation of interferences with a high-power profile for GPS based applications.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125862848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Francarl Galea, O. Casha, I. Grech, E. Gatt, J. Micallef
{"title":"Ultra Low Frequency Low Power CMOS Oscillators for MPPT and Switch Mode Power Supplies","authors":"Francarl Galea, O. Casha, I. Grech, E. Gatt, J. Micallef","doi":"10.1109/PRIME.2018.8430355","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430355","url":null,"abstract":"This paper presents the design of two low power consumption analog oscillators implemented in a $0 . 35mu mathrm {m}$ CMOS technology. These oscillators were designed for a power conditioning circuit with an analogue Perturbation and Observation (P&O) Maximum Power Point Tracker (MPPT) to maximize the scavenged power generated by energy harvesting devices. The nominal frequency of the two oscillators is 15Hz and 200kHz, respectively. The 15Hz oscillator is used to clock the MPPT, whereas the second oscillator generates a sawtooth wave required for the Pulse Width Modulation (PWM) of the switch mode converter. Both oscillators work with a supply voltage of 1V and use a reference current generated by a self-biasing zero temperature coefficient circuit. All the circuitry was designed to operate in the sub-threshold region in order to keep its power consumption to a minimum. The frequency of the 15Hz oscillator varies by $7 . 1$% over a temperature variation from −40°C to 125°C. The total power consumption including the current reference circuit is 30nW at 27°C and reaches a maximum of 90nW at 80°C. The frequency of the 200kHz oscillator varies by 33% over a temperature variation from −40°C to 125°C. The sawtooth generator, together with the current reference circuit, consume 63nW across this temperature range.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125960743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective","authors":"A. Sharma, N. Alam, B. Anand","doi":"10.1109/PRIME.2018.8430312","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430312","url":null,"abstract":"This paper examines and models the performance of mlutifinger Ultra-Thin Box and Body Fully-Depleted (UTBBFD-SOI) MOSFETs in the presence of process induced mechani- cal stress. We model the channel stress and effective drive current $(I_{eff})$ in a multifinger FDSOI MOSFET (Si channel NMOS and SiGe channel PMOS) as a function of number of fingers (NFs). The proposed $I_{eff}$ model predicts the performance (i.e., $I_{mathrm {e}ff})$ of Inverter/NAND-2/NAND-3 with a maximum error of 7% compared to Sentaurus TCAD simulations. We show that as the NFs in an NMOSFET increases from 1 to 12, $I_{mathrm {e}ff}$ per micrometer width increases by $approx ~36$% and subsequently saturates. This is due to the increase in the channel stress with the NFs, which is similar to as observed in the bulk-CMOS technology. However, due to high biaxial stress, a PMOSFET’s (SiGe channel) performance changes only marginally with the NFs. This is because the improvement in hole mobility saturates at high biaxial stress values. We also show that the FO4 delay of an inverter reduces by 16.67% when twelve-finger devices are used to design the inverter rather than single finger devices. Finally, using our stress model and $I_{eff}$ for an inverter$/mathrm {N}mathrm {A}mathrm {N}mathrm {D}/mathrm {N}mathrm {O}mathrm {R}$ cells, we propose a modified logical effort methodology (LEM) for combinational data-paths which incorporates multifinger effects in FDSOI MOSFETs. A 5-stage data-path designed using our LEM results in 14.3% improvement in total active area and 7% reduction in leakage power without a loss in speed compared to conventional technique.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121941263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Luca Sarti, Luca Baldanzi, Luca Crocetti, Berardino Carnevale, L. Fanucci
{"title":"A Simulated Approach to Evaluate Side Channel Attack Countermeasures for the Advanced Encryption Standard","authors":"Luca Sarti, Luca Baldanzi, Luca Crocetti, Berardino Carnevale, L. Fanucci","doi":"10.1109/PRIME.2018.8430344","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430344","url":null,"abstract":"Modern networks have critical security needs and a suitable level of protection and performance is usually achieved with the use of dedicated hardware cryptographic cores. Although the Advanced Encryption Standard (AES) is considered the best approach when symmetric cryptography is required, one of its main weaknesses lies in its measurable power consumption. Side Channel Attacks (SCAs) use this emitted power to analyze and revert the mathematical steps and extract the encryption key. In this work we propose a simulated methodology based on Correlation and Differential Power Analysis. Our solution extracts the simulated power from a gate-level implementation of the AES core and elaborates it using mathematical-statistical procedures. An SCA countermeasure can then be evaluated without the need for any physical circuit. Each solution can be benchmarked during an early step of the design thereby shortening the evaluation phase and helping designers to find the best solution during a preliminary phase. The cost of our approach is lower compared to any kind of analysis that requires the silicon chip to evaluate SCA protection.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Costanzo, R. Giofré, A. Salvucci, G. Polli, E. Limiti
{"title":"A 4W 37.5-42.5 GHz Power Amplifier MMIC in GaN on Si Technology","authors":"F. Costanzo, R. Giofré, A. Salvucci, G. Polli, E. Limiti","doi":"10.1109/PRIME.2018.8430333","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430333","url":null,"abstract":"the design of a Q-band high power amplifier (HPA) in Microwave Monolithic Integrated Circuit (MMIC) technology is presented. The HPA is fabricated in a 100nm gate length Gallium Nitride on Silicon (GaN-Si) technology. The HPA, based on a four-stage architecture, was designed accounting for the de-rating rules foreseen for spatial use and to work in continuous wave (CW) conditions. Nevertheless, the realized HPA can provide a saturated output power larger than 36.5dBm with a gain and a power added efficiency higher than 22dB and 30%, respectively, in the operative band from 37.5GHz to 42.5GHz. The chip area is 3.54 × 3.5 mm2. Such results are in line with others state-of-art HPAs realized in more expensive GaN processes based on Silicon Carbide, thus demonstrating that high resistivity Silicon substrate can be efficiently adopted also in such a peculiar application.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123752805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}