UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective

Abstract

This paper examines and models the performance of mlutifinger Ultra-Thin Box and Body Fully-Depleted (UTBBFD-SOI) MOSFETs in the presence of process induced mechani- cal stress. We model the channel stress and effective drive current $(I_{eff})$ in a multifinger FDSOI MOSFET (Si channel NMOS and SiGe channel PMOS) as a function of number of fingers (NFs). The proposed $I_{eff}$ model predicts the performance (i.e., $I_{\mathrm {e}ff})$ of Inverter/NAND-2/NAND-3 with a maximum error of 7% compared to Sentaurus TCAD simulations. We show that as the NFs in an NMOSFET increases from 1 to 12, $I_{\mathrm {e}ff}$ per micrometer width increases by $\approx ~36$% and subsequently saturates. This is due to the increase in the channel stress with the NFs, which is similar to as observed in the bulk-CMOS technology. However, due to high biaxial stress, a PMOSFET’s (SiGe channel) performance changes only marginally with the NFs. This is because the improvement in hole mobility saturates at high biaxial stress values. We also show that the FO4 delay of an inverter reduces by 16.67% when twelve-finger devices are used to design the inverter rather than single finger devices. Finally, using our stress model and $I_{eff}$ for an inverter$/\mathrm {N}\mathrm {A}\mathrm {N}\mathrm {D}/\mathrm {N}\mathrm {O}\mathrm {R}$ cells, we propose a modified logical effort methodology (LEM) for combinational data-paths which incorporates multifinger effects in FDSOI MOSFETs. A 5-stage data-path designed using our LEM results in 14.3% improvement in total active area and 7% reduction in leakage power without a loss in speed compared to conventional technique.