{"title":"A Variability-Aware Analysis and Design Guideline for Write and Read Operations in Crosspoint STT-MRAM Arrays","authors":"Y. A. Belay, A. Cabrini, G. Torelli","doi":"10.1109/PRIME.2018.8430358","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430358","url":null,"abstract":"Beneliting from emerging resistance-switching mem- ory technologies, crosspoint array has become an attractive array architecture to obtain high storage density. Among the emerging technologies, Spin-Transfer Torque magnetic memory (STT-MRAM) is a potential candidate as storage class memory (SCM) or static/dynamic RAM replacement due to its high write speed, scalability and other interesting characteristics. In this paper, we present a variation-aware comprehensive analysis of the boundary conditions for write and read requirements for the implementation of crosspoint STT-MRAM Arrays. The results of the analysis are very useful as design guide and for choosing a suitable selector device for Crosspoint STT-MRAM arrays.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124609818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a Low-power Ultrasound Transceiver for Underwater Sensor Networks","authors":"Gönenç Berkol, P. Baltus, P. Harpe, E. Cantatore","doi":"10.1109/PRIME.2018.8430305","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430305","url":null,"abstract":"This paper presents an ultrasound (US) transceiver including a transmitter and a receiver for underwater wireless sensor nodes, where low-power operation is desired to extend the life-time of the network. A system-level analysis of the underwater communication has been performed by taking into account the underwater propagation and the medium charac- teristics to show their impact on the overall performance. In addition, a low-noise amplffier using an inverter-based topology has been introduced to ensure power efficiency of the receiver, where a bulk-feedback method is proposed to stabilize the output bias point of the inverter. Simulation results show that the proposed transceiver has a scalable power consumption from $1.95mu W$ to $10.4mu W$ while achieving $100mu V$ to $20mu V$ sensitivity at a $10^{-3}$ BER level.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Real Time Defect Detection of Wheel Bearing by Means of a Wirelessly Connected Microphone","authors":"Erica Raviola, F. Fiori","doi":"10.1109/PRIME.2018.8430303","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430303","url":null,"abstract":"In this work, an electronic system aiming to automatically monitor the state of health of wheel bearings, is proposed. The focus is on designing a low cost, smallsize and wirelessly interfaced module. Acoustic emissions are exploited to detect defects by means of a low cost micro electro-mechanical system (MEMS) microphone. Amicrocontroller was used to evaluate the frequency spectrum and to interface the system through a wireless data link. The designed module successfully achieved the proposed goals. Finally, a novel measurement process is presented to evaluate the system performance under realistic conditions.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132115383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rodrigo Granja, Mauro Santos, J. Guilherme, N. Horta
{"title":"11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology","authors":"Rodrigo Granja, Mauro Santos, J. Guilherme, N. Horta","doi":"10.1109/PRIME.2018.8430374","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430374","url":null,"abstract":"This paper describes a high-resolution 11.7b Time-to-Digital Converter (TDC) designed in a pure digital CMOS 130nm technology. The target architecture comprises a looped delay-line based on an inverter-based pulse-shrinking technique. The proposed technique can achieve a 0.82ps resolution with a dynamic range of 2.918ns, an integral nonlinearity (INL) of −2.4 to 2.11 and a differential nonlinearity (DNL) of −0.91 to 0.87 LSB. In addition, it occupies a low area of 0.148 mm2.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128389421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Katsumi Inoue, Trong-Thuc Hoang, Xuan-Thuan Nguyen, Hong-Thu Nguyen, C. Pham
{"title":"VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study","authors":"Katsumi Inoue, Trong-Thuc Hoang, Xuan-Thuan Nguyen, Hong-Thu Nguyen, C. Pham","doi":"10.1109/PRIME.2018.8430308","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430308","url":null,"abstract":"In this paper, the Very-Large-Scale Integration design of Frequent Items Counting (FIC) is proposed. The fundamental idea is to use binary decoders to generate a matrix of binary values of all input items, with each column represents for one items binary value. Then, the sums are executed on the rows of the matrix to retrieve the input items counting results. The proposed design is applied to the case-study of 8bit/item. That means 256 different types of items in total. For storing the counting results, various options of count-register are also presented. The proposed architecture is implemented with seven option of count-register from 8-bit counter to 32-bit counters, with the incremental of 4-bit at a time. The design was implemented on the Altera Arria V SoC Development Kit. After successful built and verified on Field Programmable Gate Array (FPGA), the design was synthesized using Synopsys tools with the process of SOTB (Silicon on Thin Buried-oxide) 65nm. The FPGA results achieved the average speed of 3,883.1 and 4,638.62 million item-counting per second for the 32-bit and 8-bit count-register options, respectively. Compared to our previous work and the software-based application, the achieved speed results are more than three times and more than 150 times faster, respectively. The SOTB-65nm builds achieved the theory speed about 75% of the average practical results of FPGA implementations.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116759837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tobias Saalfeld, Alexander Meyer, Eva Schulte Bocholt, R. Wunderlich, S. Heinen
{"title":"Analysis of Gain and Bandwidth Limitations of Operational Amplifiers in Sigma-Delta Modulators","authors":"Tobias Saalfeld, Alexander Meyer, Eva Schulte Bocholt, R. Wunderlich, S. Heinen","doi":"10.1109/PRIME.2018.8430341","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430341","url":null,"abstract":"In Sigma-Delta modulator system design the loop filter coefficients are calculated based on ideal circuit behavior. Advancing to an actual circuit implementation based on opera- tional amplifiers, which show finite gain bandwidth products, a deviation of these coefficients is observed. These influences which were not considered during initial coefficient development can lead to performance degradation or even instability. This paper presents an analysis of the influence of the $3~mathrm {d}mathrm {B}$ bandwidth and the DC gain of an opamp to the signal and noise transfer function of a third order Sigma-Delta modulator. Based on a mathematical analysis of the transfer functions the opamp’s influences on a complex integrator and a Tow-Thomas biquad are discussed in order to give a target specification for a circuit implementation.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122256348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PRIME 2018 Events Page","authors":"","doi":"10.1109/prime.2018.8430337","DOIUrl":"https://doi.org/10.1109/prime.2018.8430337","url":null,"abstract":"","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"32 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130401816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PRIME 2018 Plenaries Page","authors":"","doi":"10.1109/prime.2018.8430373","DOIUrl":"https://doi.org/10.1109/prime.2018.8430373","url":null,"abstract":"","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":" 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120826752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Elmira Shahrabi, C. Giovinazzo, J. Sandrini, Y. Leblebici
{"title":"The key impact of incorporated Al2O3 barrier layer on W-based ReRAM switching performance","authors":"Elmira Shahrabi, C. Giovinazzo, J. Sandrini, Y. Leblebici","doi":"10.1109/PRIME.2018.8430371","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430371","url":null,"abstract":"In this article, we inspected the bipolar resistive switching behavior of W-based ReRAMs, using HfO<inf>2</inf> as switching layer. We have shown that the switching properties can be significantly enhanced by incorporating an Al<inf>2</inf>O<inf>3</inf> layer as a barrier layer. It stabilizes the resistance states and lowers the operating current. Al<inf>2</inf>O<inf>3</inf> acts as an oxygen scavenging blocking layer at W sides, results in the filament path constriction at the Al<inf>2</inf>O<inf>3</inf> HfO<inf>2</inf> interface. This leads to the more controllable reset operation and consecutively the HRS properties improvement. This allows the W/Al<inf>2</inf>O<inf>3</inf> HfO<inf>2</inf>/Pt to switch at 10 times lower operating current of 100 μA and 2 times higher memory window compared to the W/HfO<inf>2</inf>/Pt stacks. The LRS conduction of devices with the barrier layer is in perfect agreement with the Poole-Frenkel model.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121440626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Plinio Bau, M. Cousineau, B. Cougo, F. Richardeau, D. Colin, N. Rouger
{"title":"A CMOS gate driver with ultra-fast dV/dt embedded control dedicated to optimum EMI and turn-on losses management for GaN power transistors","authors":"Plinio Bau, M. Cousineau, B. Cougo, F. Richardeau, D. Colin, N. Rouger","doi":"10.1109/PRIME.2018.8430331","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430331","url":null,"abstract":"In this paper, a CMOS gate driver in $180mathrm {n}mathrm {m}$ technology is presented. The gate driver implements an integrated and independent ultra-fast $mathrm {d}mathrm {V}/mathrm {d}mathrm {t}$ control circuit dedicated to manage switch-on transients for $mathrm {G}mathrm {a}mathrm {N}$ HEMT technology. In order to mitigate a detrimental effect in EMI spectrum for wide bandgap transistors, a novel method to reduce $mathrm {d}mathrm {V}/mathrm {d}mathrm {t}$ without increasing so much switching losses is proposed. A comprehensive benchmark with the classical method is also presented, where the gate driver resistance is typically adjusted. Simulations are conducted to show the feasibility of the proposed method and the amount of switching energy that can be saved. Time responses of a feedback loop lower than $200mathrm {p}mathrm {s}$ are expected. The preliminary characterization of the integrated CMOS circuit is shown.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115649580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}