Claudio Nocera, Andrea Cavarra, E. Ragonese, G. Palmisano, G. Papotto
{"title":"Down-converter solutions for 77-GHz automotive radar sensors in 28-nm FD-SOI CMOS technology","authors":"Claudio Nocera, Andrea Cavarra, E. Ragonese, G. Palmisano, G. Papotto","doi":"10.1109/PRIME.2018.8430319","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430319","url":null,"abstract":"This paper presents a review of 77-GHz down-converter solutions for automotive radar sensors in 28-nm FD-SOI CMOS technology. A comparison of two different topologies based on common source (CS) and common gate (CG) stages is reported. The comparison is carried out at a power supply as low as 1-V and at 15-mA current consumption. CS-based and CG-based down-converters achieve a conversion gain of 27.5 and 21.3 dB over a −3-dB bandwidth of 16 GHz and 22 GHz, respectively, while exhibiting a noise figure of 7.8 dB and 9.1 dB.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117315305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Andrea Ria, S. D. Cesta, A. Catania, M. Piotto, P. Bruschi
{"title":"Improved class-AB output stage for Sub-1 V fully-differential operational amplifiers","authors":"Andrea Ria, S. D. Cesta, A. Catania, M. Piotto, P. Bruschi","doi":"10.1109/PRIME.2018.8430361","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430361","url":null,"abstract":"An existent architecture for low voltage class-AB output stages is analyzed finding critical issues for which effective original solutions are proposed. The approach has been applied to the design of a compact class-AB fully-differential operational amplifier, capable of operating at a supply voltage of 0.8 V, providing a maximum output current of 7.5 mA with only 156 uA of quiescent supply current. The proposed amplifier constitutes a convenient building block for switched-capacitor circuits and low-voltage sensor interfaces. The performances of the amplifier are demonstrated by means of electrical simulations performed on a prototype designed with the UMC 0.18 $mu {mathrm{ m}}$ CMOS process. The total estimated area of the cell is 0.023 mm$^{mathbf {2}}$.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115037729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pascal Raffelberg, Roman Burkard, R. Viga, W. Mokwa, P. Walter, A. Grabmaier, R. Kokozinski
{"title":"Current Controlled CMOS Stimulator with Programmable Pulse Pattern for a Retina Implant","authors":"Pascal Raffelberg, Roman Burkard, R. Viga, W. Mokwa, P. Walter, A. Grabmaier, R. Kokozinski","doi":"10.1109/PRIME.2018.8430332","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430332","url":null,"abstract":"In this work the constant current stimulator of a new epiretinal implant is presented. It consists of a digital waveform generator device, which permits to modify the pulse pattern via a programming interface, a digital–to–current converter, which translates the digital waveform into current pulses with adjustable amplitude, and an output driver, which combines the function of an electrode multiplexer and a high voltage current source for driving large resistive loads. For each of those subcircuits the simulated performance and its designed layout is presented.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125519670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Nannipieri, Gianmarco Dinelli, Daniele Davalle, L. Fanucci
{"title":"A SpaceFibre multi lane codec System on a Chip: enabling technology for low cost satellite EGSE","authors":"P. Nannipieri, Gianmarco Dinelli, Daniele Davalle, L. Fanucci","doi":"10.1109/PRIME.2018.8430317","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430317","url":null,"abstract":"In the last few years, data rate requirement on on-board satellite communication systems significantly grown. The need of high speed networks led to the birth of the SpaceFibre protocol, which is able to run at several Gigabit per second and operates over both optical fibre and copper cables. A key feature of SpaceFibre is the possibility to have multi lane link, which increases the overall achievable data rate and link reliability. The growing complexity of satellite payload communication systems requires the definition an accurate monitoring and testing system. In this paper a multi lane SpaceFibre interface integrated in a System on a Chip is presented as enabling technology for an electrical ground segment equipment.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124480008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A ZTC-based 0.5V CMOS Voltage Reference","authors":"Y. Wenger, B. Meinerzhagen","doi":"10.1109/PRIME.2018.8430368","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430368","url":null,"abstract":"This paper presents a voltage reference circuit operational from a 0.5 V supply which is based on the zero-temperature coefficient (ZTC) operating point of a MOS transistor. The ZTC condition is reviewed and it is found that a MOSFET biased below its ZTC point with a PTAT current source can yield a temperature stable output at this low supply voltage. With this idea in mind, a circuit which does not rely on the availability of special devices like Shottky diodes is designed in 130 nm CMOS. Simulations show that this circuit generates an average reference voltage of 318 mV from a 0.5 V supply. The temperature coefficient is 154 ppm/K and the voltage reference has a power supply rejection ratio (PSRR) of 41 dB at DC.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126280574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Arnau Salas Barenys, N. Vidal, J. Sieiro, J. López-Villegas, B. Medina-Rodriguez, F. Ramos
{"title":"Fabrication of Full-3D Printed Electronics RF Passive Components and Circuits","authors":"Arnau Salas Barenys, N. Vidal, J. Sieiro, J. López-Villegas, B. Medina-Rodriguez, F. Ramos","doi":"10.1109/PRIME.2018.8430356","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430356","url":null,"abstract":"This paper presents a process for full-3D circuit and RF passive component fabrication based on two main steps: additive manufacturing of the plastic or ceramic substrate, through a stereolitographic 3D printer, and a copper electroless plating metallization process. The metallization results are discussed in terms of resistivity, comparing them to the State-of-the-Art on 3D printed electronics. The capabilities and accuracy of the process have been demonstrated and discussed through the fabrication of conical inductors.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125157406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A High-resolution Δ-Modulator ADC with Oversampling and Noise-shaping for IoT","authors":"Ana Correia, P. Barquinha, Joao Marques, J. Goes","doi":"10.1109/PRIME.2018.8430338","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430338","url":null,"abstract":"This paper proposes a novel high-resolution delta-modulator with oversampling and noise-shaping suitable for industrial IoT systems. “Inspired by” a SAR ADC, this architecture uses an integrator in the digital domain, instead of the usual SAR logic. Combining adaptive-step delta-modulation with the adopted low/medium-resolution DAC scheme, an energy efficient A/D converter architecture is proposed, presenting encouraging results in comparison with the reported SAR algorithms. Behavioral simulations demonstrate a dynamic performance of 88 dB of SNDR, corresponding to an ENOB of 14.3 bits, for a 1 MHz input signal bandwidth and using an oversampling-ratio of 64.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128493674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Generalization of Referenceless Timing Mismatch Calibration Methods for Time-Interleaved ADCs","authors":"Arda Uran, Mustafa Kilic, Y. Leblebici","doi":"10.1109/PRIME.2018.8430340","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430340","url":null,"abstract":"Calibration of time-interleaved analog-to-digital converters is a problem whose necessity and complexity increase with the number of interleaved channels. In this study, we develop a generic representation of the referenceless timing mismatch calibration scheme for N-channel TI-ADCs. We compare cross-correlation and mean absolute difference based approaches, and investigate the effect of increasing number of channels on the performance. We use both mathematical analyses and simulations to reveal degradation mechanisms, and discuss the extent to which this scheme is applicable.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131394735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling of a capacitive sensor dedicated to drug injection","authors":"Sylvain Joly, A. Lepple-Wienhues, C. Dehollain","doi":"10.1109/PRIME.2018.8430369","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430369","url":null,"abstract":"to follow up patients who inject themselves insulin with injection pen is a quite complex task. Due to the repetition of injections, and the numerous influent parameter the patient can easily made an injection mistake and it is difficult for health-takers to follow these injections and can detect errors. In order to compensate this problem, a device which measures the volume of drug by using electric fields has been developed. A theoretical model, simulations and experiments have been conducted to validate this capacitive measurement technique. The experiments confirm Theory and simulations results. A sensitivity around 5fF for lOuL have been found and a good repeatability between three caps have been achieved which is equal to an error of 0.44fF for lOuL of insulin and correspond to an error of ±4.12%.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132826486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electric Vehicle Battery Management System Using Power Line Communication Technique","authors":"A. P. Talei, W. Pribyl, G. Hofer","doi":"10.1109/PRIME.2018.8430304","DOIUrl":"https://doi.org/10.1109/PRIME.2018.8430304","url":null,"abstract":"this paper presents the analysis and test of a power line communication system targeting the communication between each battery cell and the battery management system located in an electric vehicle. The battery cell type which is used for analysis and for the lab measurement is 18650 and the objective is to use a stack of batteries as a channel to transmit and receive digital data with high data rate using FSK modulation with 10MHZ carrier frequency.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"32 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116344706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}