11.7b时间-数字转换器，分辨率为0.82ps，采用130nm CMOS技术

2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2018-07-01 DOI:10.1109/PRIME.2018.8430374

Rodrigo Granja, Mauro Santos, J. Guilherme, N. Horta

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引用次数: 2

摘要

本文介绍了一种采用纯数字CMOS 130nm技术设计的高分辨率11.7b时间-数字转换器(TDC)。目标结构包括一个基于逆变器脉冲收缩技术的环形延迟线。该技术可实现0.82ps的分辨率，动态范围为2.918ns，积分非线性(INL)为−2.4 ~ 2.11，微分非线性(DNL)为−0.91 ~ 0.87 LSB。此外，它占用0.148 mm2的低面积。

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11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology

This paper describes a high-resolution 11.7b Time-to-Digital Converter (TDC) designed in a pure digital CMOS 130nm technology. The target architecture comprises a looped delay-line based on an inverter-based pulse-shrinking technique. The proposed technique can achieve a 0.82ps resolution with a dynamic range of 2.918ns, an integral nonlinearity (INL) of −2.4 to 2.11 and a differential nonlinearity (DNL) of −0.91 to 0.87 LSB. In addition, it occupies a low area of 0.148 mm2.

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2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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